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Add testcase for RRX and ASRS (which effectively tests MOVs, since those

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are just forms of that instruction).

llvm-svn: 116538
This commit is contained in:
Jim Grosbach 2010-10-14 23:29:18 +00:00
parent 6da1b52d7b
commit 26842cb893
1 changed files with 8 additions and 0 deletions
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8
test/MC/ARM/simple-encoding.ll
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@ -90,5 +90,13 @@ entry:
ret i32 42405
}
define i64 @f10(i64 %a) nounwind readnone ssp {
entry:
; CHECK: f10
; CHECK: asrs r1, r1, #1 @ encoding: [0xc1,0x10,0xb0,0xe1]
; CHECK: rrx r0, r0 @ encoding: [0x60,0x00,0xa0,0xe1]
%shr = ashr i64 %a, 1
ret i64 %shr
}
declare void @llvm.trap() nounwind