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eliminate the last DOUTs from the targets.

Browse Source 
llvm-svn: 79833
This commit is contained in:
Chris Lattner 2009-08-23 06:49:22 +00:00
parent 89d3d59e83
commit 26ec3291f0
12 changed files with 112 additions and 164 deletions
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21
lib/Target/ARM/ARMCodeEmitter.cpp
View File

@ -316,21 +316,15 @@ void Emitter<CodeEmitter>::emitMachineBasicBlock(MachineBasicBlock *BB,
template<class CodeEmitter>
void Emitter<CodeEmitter>::emitWordLE(unsigned Binary) {
#ifndef NDEBUG
DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
<< Binary << std::dec << "\n";
#endif
DEBUG(errs() << " 0x";
errs().write_hex(Binary) << "\n");
MCE.emitWordLE(Binary);
}
template<class CodeEmitter>
void Emitter<CodeEmitter>::emitDWordLE(uint64_t Binary) {
#ifndef NDEBUG
DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
<< (unsigned)Binary << std::dec << "\n";
DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
<< (unsigned)(Binary >> 32) << std::dec << "\n";
#endif
DEBUG(errs() << " 0x";
errs().write_hex(Binary) << "\n");
MCE.emitDWordLE(Binary);
}
@ -582,8 +576,8 @@ void Emitter<CodeEmitter>::emitPseudoMoveInstruction(const MachineInstr &MI) {
template<class CodeEmitter>
void Emitter<CodeEmitter>::addPCLabel(unsigned LabelID) {
DOUT << " ** LPC" << LabelID << " @ "
<< (void*)MCE.getCurrentPCValue() << '\n';
DEBUG(errs() << " ** LPC" << LabelID << " @ "
<< (void*)MCE.getCurrentPCValue() << '\n');
JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
}
@ -1145,7 +1139,8 @@ void Emitter<CodeEmitter>::emitInlineJumpTable(unsigned JTIndex) {
// Remember the base address of the inline jump table.
uintptr_t JTBase = MCE.getCurrentPCValue();
JTI->addJumpTableBaseAddr(JTIndex, JTBase);
DOUT << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase << '\n';
DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
<< '\n');
// Now emit the jump table entries.
const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;

26
lib/Target/ARM/ARMConstantIslandPass.cpp
View File

@ -217,8 +217,8 @@ void ARMConstantIslands::verify(MachineFunction &MF) {
/// print block size and offset information - debugging
void ARMConstantIslands::dumpBBs() {
for (unsigned J = 0, E = BBOffsets.size(); J !=E; ++J) {
DOUT << "block " << J << " offset " << BBOffsets[J] <<
" size " << BBSizes[J] << "\n";
DEBUG(errs() << "block " << J << " offset " << BBOffsets[J]
<< " size " << BBSizes[J] << "\n");
}
}
@ -351,7 +351,8 @@ void ARMConstantIslands::DoInitialPlacement(MachineFunction &MF,
CPEs.push_back(CPEntry(CPEMI, i));
CPEntries.push_back(CPEs);
NumCPEs++;
DOUT << "Moved CPI#" << i << " to end of function as #" << i << "\n";
DEBUG(errs() << "Moved CPI#" << i << " to end of function as #" << i
<< "\n");
}
}
@ -878,7 +879,7 @@ int ARMConstantIslands::LookForExistingCPEntry(CPUser& U, unsigned UserOffset)
// Check to see if the CPE is already in-range.
if (CPEIsInRange(UserMI, UserOffset, CPEMI, U.MaxDisp, U.NegOk, true)) {
DOUT << "In range\n";
DEBUG(errs() << "In range\n");
return 1;
}
@ -893,7 +894,8 @@ int ARMConstantIslands::LookForExistingCPEntry(CPUser& U, unsigned UserOffset)
if (CPEs[i].CPEMI == NULL)
continue;
if (CPEIsInRange(UserMI, UserOffset, CPEs[i].CPEMI, U.MaxDisp, U.NegOk)) {
DOUT << "Replacing CPE#" << CPI << " with CPE#" << CPEs[i].CPI << "\n";
DEBUG(errs() << "Replacing CPE#" << CPI << " with CPE#"
<< CPEs[i].CPI << "\n");
// Point the CPUser node to the replacement
U.CPEMI = CPEs[i].CPEMI;
// Change the CPI in the instruction operand to refer to the clone.
@ -931,7 +933,7 @@ static inline unsigned getUnconditionalBrDisp(int Opc) {
MachineBasicBlock* ARMConstantIslands::AcceptWater(MachineBasicBlock *WaterBB,
std::vector<MachineBasicBlock*>::iterator IP) {
DOUT << "found water in range\n";
DEBUG(errs() << "found water in range\n");
// Remove the original WaterList entry; we want subsequent
// insertions in this vicinity to go after the one we're
// about to insert. This considerably reduces the number
@ -1010,7 +1012,7 @@ void ARMConstantIslands::CreateNewWater(unsigned CPUserIndex,
if (&UserMBB->back() == UserMI ||
OffsetIsInRange(UserOffset, OffsetOfNextBlock + (isThumb1 ? 2: 4),
U.MaxDisp, U.NegOk, U.IsSoImm)) {
DOUT << "Split at end of block\n";
DEBUG(errs() << "Split at end of block\n");
if (&UserMBB->back() == UserMI)
assert(BBHasFallthrough(UserMBB) && "Expected a fallthrough BB!");
*NewMBB = next(MachineFunction::iterator(UserMBB));
@ -1075,7 +1077,7 @@ void ARMConstantIslands::CreateNewWater(unsigned CPUserIndex,
CPUIndex++;
}
}
DOUT << "Split in middle of big block\n";
DEBUG(errs() << "Split in middle of big block\n");
*NewMBB = SplitBlockBeforeInstr(prior(MI));
}
}
@ -1112,7 +1114,7 @@ bool ARMConstantIslands::HandleConstantPoolUser(MachineFunction &MF,
if (!LookForWater(U, UserOffset, &NewMBB)) {
// No water found.
DOUT << "No water found\n";
DEBUG(errs() << "No water found\n");
CreateNewWater(CPUserIndex, UserOffset, &NewMBB);
}
@ -1324,9 +1326,9 @@ ARMConstantIslands::FixUpConditionalBr(MachineFunction &MF, ImmBranch &Br) {
}
MachineBasicBlock *NextBB = next(MachineFunction::iterator(MBB));
DOUT << " Insert B to BB#" << DestBB->getNumber()
<< " also invert condition and change dest. to BB#"
<< NextBB->getNumber() << "\n";
DEBUG(errs() << " Insert B to BB#" << DestBB->getNumber()
<< " also invert condition and change dest. to BB#"
<< NextBB->getNumber() << "\n");
// Insert a new conditional branch and a new unconditional branch.
// Also update the ImmBranch as well as adding a new entry for the new branch.

35
lib/Target/Alpha/AlphaJITInfo.cpp
View File

@ -19,6 +19,7 @@
#include "llvm/Config/alloca.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include <cstdlib>
using namespace llvm;
@ -58,12 +59,12 @@ static void EmitBranchToAt(void *At, void *To) {
AtI[0] = BUILD_OR(0, 27, 27);
DOUT << "Stub targeting " << To << "\n";
DEBUG(errs() << "Stub targeting " << To << "\n");
for (int x = 1; x <= 8; ++x) {
AtI[2*x - 1] = BUILD_SLLi(27,27,8);
unsigned d = (Fn >> (64 - 8 * x)) & 0x00FF;
//DOUT << "outputing " << hex << d << dec << "\n";
//DEBUG(errs() << "outputing " << hex << d << dec << "\n");
AtI[2*x] = BUILD_ORi(27, 27, d);
}
AtI[17] = BUILD_JMP(31,27,0); //jump, preserving ra, and setting pv
@ -87,12 +88,12 @@ extern "C" {
//rewrite the stub to an unconditional branch
if (((unsigned*)CameFromStub)[18] == 0x00FFFFFF) {
DOUT << "Came from a stub, rewriting\n";
DEBUG(errs() << "Came from a stub, rewriting\n");
EmitBranchToAt(CameFromStub, Target);
} else {
DOUT << "confused, didn't come from stub at " << CameFromStub
<< " old jump vector " << oldpv
<< " new jump vector " << Target << "\n";
DEBUG(errs() << "confused, didn't come from stub at " << CameFromStub
<< " old jump vector " << oldpv
<< " new jump vector " << Target << "\n");
}
//Change pv to new Target
@ -199,7 +200,7 @@ void *AlphaJITInfo::emitFunctionStub(const Function* F, void *Fn,
for (int x = 0; x < 19; ++ x)
JCE.emitWordLE(0);
EmitBranchToAt(Addr, Fn);
DOUT << "Emitting Stub to " << Fn << " at [" << Addr << "]\n";
DEBUG(errs() << "Emitting Stub to " << Fn << " at [" << Addr << "]\n");
return JCE.finishGVStub(F);
}
@ -245,30 +246,30 @@ void AlphaJITInfo::relocate(void *Function, MachineRelocation *MR,
case Alpha::reloc_literal:
//This is a LDQl
idx = MR->getGOTIndex();
DOUT << "Literal relocation to slot " << idx;
DEBUG(errs() << "Literal relocation to slot " << idx);
idx = (idx - GOToffset) * 8;
DOUT << " offset " << idx << "\n";
DEBUG(errs() << " offset " << idx << "\n");
break;
case Alpha::reloc_gprellow:
idx = (unsigned char*)MR->getResultPointer() - &GOTBase[GOToffset * 8];
idx = getLower16(idx);
DOUT << "gprellow relocation offset " << idx << "\n";
DOUT << " Pointer is " << (void*)MR->getResultPointer()
<< " GOT is " << (void*)&GOTBase[GOToffset * 8] << "\n";
DEBUG(errs() << "gprellow relocation offset " << idx << "\n");
DEBUG(errs() << " Pointer is " << (void*)MR->getResultPointer()
<< " GOT is " << (void*)&GOTBase[GOToffset * 8] << "\n");
break;
case Alpha::reloc_gprelhigh:
idx = (unsigned char*)MR->getResultPointer() - &GOTBase[GOToffset * 8];
idx = getUpper16(idx);
DOUT << "gprelhigh relocation offset " << idx << "\n";
DOUT << " Pointer is " << (void*)MR->getResultPointer()
<< " GOT is " << (void*)&GOTBase[GOToffset * 8] << "\n";
DEBUG(errs() << "gprelhigh relocation offset " << idx << "\n");
DEBUG(errs() << " Pointer is " << (void*)MR->getResultPointer()
<< " GOT is " << (void*)&GOTBase[GOToffset * 8] << "\n");
break;
case Alpha::reloc_gpdist:
switch (*RelocPos >> 26) {
case 0x09: //LDAH
idx = &GOTBase[GOToffset * 8] - (unsigned char*)RelocPos;
idx = getUpper16(idx);
DOUT << "LDAH: " << idx << "\n";
DEBUG(errs() << "LDAH: " << idx << "\n");
//add the relocation to the map
gpdistmap[std::make_pair(Function, MR->getConstantVal())] = RelocPos;
break;
@ -278,7 +279,7 @@ void AlphaJITInfo::relocate(void *Function, MachineRelocation *MR,
idx = &GOTBase[GOToffset * 8] -
(unsigned char*)gpdistmap[std::make_pair(Function, MR->getConstantVal())];
idx = getLower16(idx);
DOUT << "LDA: " << idx << "\n";
DEBUG(errs() << "LDA: " << idx << "\n");
break;
default:
llvm_unreachable("Cannot handle gpdist yet");

10
lib/Target/Alpha/AlphaRegisterInfo.cpp
View File

@ -174,16 +174,16 @@ void AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
// Now add the frame object offset to the offset from the virtual frame index.
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
DOUT << "FI: " << FrameIndex << " Offset: " << Offset << "\n";
DEBUG(errs() << "FI: " << FrameIndex << " Offset: " << Offset << "\n");
Offset += MF.getFrameInfo()->getStackSize();
DOUT << "Corrected Offset " << Offset
<< " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n";
DEBUG(errs() << "Corrected Offset " << Offset
<< " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n");
if (Offset > IMM_HIGH || Offset < IMM_LOW) {
DOUT << "Unconditionally using R28 for evil purposes Offset: "
<< Offset << "\n";
DEBUG(errs() << "Unconditionally using R28 for evil purposes Offset: "
<< Offset << "\n");
//so in this case, we need to use a temporary register, and move the
//original inst off the SP/FP
//fix up the old:

2
lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp
View File

@ -77,7 +77,7 @@ FunctionPass *llvm::createBlackfinISelDag(BlackfinTargetMachine &TM,
void BlackfinDAGToDAGISel::InstructionSelect() {
// Select target instructions for the DAG.
SelectRoot(*CurDAG);
DOUT << "Selected selection DAG before regclass fixup:\n";
DEBUG(errs() << "Selected selection DAG before regclass fixup:\n");
DEBUG(CurDAG->dump());
FixRegisterClasses(*CurDAG);
}

7
lib/Target/CellSPU/SPUHazardRecognizers.cpp
View File

@ -20,7 +20,7 @@
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
//===----------------------------------------------------------------------===//
@ -115,7 +115,8 @@ SPUHazardRecognizer::getHazardType(SUnit *SU)
if (mustBeOdd && !EvenOdd)
retval = Hazard;
DOUT << "SPUHazardRecognizer EvenOdd " << EvenOdd << " Hazard " << retval << "\n";
DEBUG(errs() << "SPUHazardRecognizer EvenOdd " << EvenOdd << " Hazard "
<< retval << "\n");
EvenOdd ^= 1;
return retval;
#else
@ -129,7 +130,7 @@ void SPUHazardRecognizer::EmitInstruction(SUnit *SU)
void SPUHazardRecognizer::AdvanceCycle()
{
DOUT << "SPUHazardRecognizer::AdvanceCycle\n";
DEBUG(errs() << "SPUHazardRecognizer::AdvanceCycle\n");
}
void SPUHazardRecognizer::EmitNoop()

28
lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
View File

@ -129,14 +129,10 @@ void MSP430DAGToDAGISel::InstructionSelect() {
DEBUG(BB->dump());
// Codegen the basic block.
#ifndef NDEBUG
DOUT << "===== Instruction selection begins:\n";
DEBUG(errs() << "===== Instruction selection begins:\n");
Indent = 0;
#endif
SelectRoot(*CurDAG);
#ifndef NDEBUG
DOUT << "===== Instruction selection ends:\n";
#endif
DEBUG(errs() << "===== Instruction selection ends:\n");
CurDAG->RemoveDeadNodes();
}
@ -146,21 +142,17 @@ SDNode *MSP430DAGToDAGISel::Select(SDValue Op) {
DebugLoc dl = Op.getDebugLoc();
// Dump information about the Node being selected
#ifndef NDEBUG
DOUT << std::string(Indent, ' ') << "Selecting: ";
DEBUG(errs().indent(Indent) << "Selecting: ");
DEBUG(Node->dump(CurDAG));
DOUT << "\n";
DEBUG(errs() << "\n");
Indent += 2;
#endif
// If we have a custom node, we already have selected!
if (Node->isMachineOpcode()) {
#ifndef NDEBUG
DOUT << std::string(Indent-2, ' ') << "== ";
DEBUG(Node->dump(CurDAG));
DOUT << "\n";
DEBUG(errs().indent(Indent-2) << "== ";
Node->dump(CurDAG);
errs() << "\n");
Indent -= 2;
#endif
return NULL;
}
@ -182,15 +174,13 @@ SDNode *MSP430DAGToDAGISel::Select(SDValue Op) {
// Select the default instruction
SDNode *ResNode = SelectCode(Op);
#ifndef NDEBUG
DOUT << std::string(Indent-2, ' ') << "=> ";
DEBUG(errs() << std::string(Indent-2, ' ') << "=> ");
if (ResNode == NULL || ResNode == Op.getNode())
DEBUG(Op.getNode()->dump(CurDAG));
else
DEBUG(ResNode->dump(CurDAG));
DOUT << "\n";
DEBUG(errs() << "\n");
Indent -= 2;
#endif
return ResNode;
}

38
lib/Target/Mips/MipsISelDAGToDAG.cpp
View File

@ -108,22 +108,16 @@ private:
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
void MipsDAGToDAGISel::
InstructionSelect()
{
void MipsDAGToDAGISel::InstructionSelect() {
DEBUG(BB->dump());
// Codegen the basic block.
#ifndef NDEBUG
DOUT << "===== Instruction selection begins:\n";
DEBUG(errs() << "===== Instruction selection begins:\n");
Indent = 0;
#endif
// Select target instructions for the DAG.
SelectRoot(*CurDAG);
#ifndef NDEBUG
DOUT << "===== Instruction selection ends:\n";
#endif
DEBUG(errs() << "===== Instruction selection ends:\n");
CurDAG->RemoveDeadNodes();
}
@ -187,29 +181,23 @@ SelectAddr(SDValue Op, SDValue Addr, SDValue &Offset, SDValue &Base)
/// Select instructions not customized! Used for
/// expanded, promoted and normal instructions
SDNode* MipsDAGToDAGISel::
Select(SDValue N)
{
SDNode* MipsDAGToDAGISel::Select(SDValue N) {
SDNode *Node = N.getNode();
unsigned Opcode = Node->getOpcode();
DebugLoc dl = Node->getDebugLoc();
// Dump information about the Node being selected
#ifndef NDEBUG
DOUT << std::string(Indent, ' ') << "Selecting: ";
DEBUG(Node->dump(CurDAG));
DOUT << "\n";
DEBUG(errs().indent(Indent) << "Selecting: ";
Node->dump(CurDAG);
errs() << "\n");
Indent += 2;
#endif
// If we have a custom node, we already have selected!
if (Node->isMachineOpcode()) {
#ifndef NDEBUG
DOUT << std::string(Indent-2, ' ') << "== ";
DEBUG(Node->dump(CurDAG));
DOUT << "\n";
DEBUG(errs().indent(Indent-2) << "== ";
Node->dump(CurDAG);
errs() << "\n");
Indent -= 2;
#endif
return NULL;
}
@ -373,15 +361,13 @@ Select(SDValue N)
// Select the default instruction
SDNode *ResNode = SelectCode(N);
#ifndef NDEBUG
DOUT << std::string(Indent-2, ' ') << "=> ";
DEBUG(errs().indent(Indent-2) << "=> ");
if (ResNode == NULL || ResNode == N.getNode())
DEBUG(N.getNode()->dump(CurDAG));
else
DEBUG(ResNode->dump(CurDAG));
DOUT << "\n";
DEBUG(errs() << "\n");
Indent -= 2;
#endif
return ResNode;
}

20
lib/Target/Mips/MipsRegisterInfo.cpp
View File

@ -362,31 +362,23 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
"Instr doesn't have FrameIndex operand!");
}
#ifndef NDEBUG
DEBUG(errs() << "\nFunction : " << MF.getFunction()->getName() << "\n");
DEBUG(errs() << "<--------->\n");
DEBUG(MI.print(errs()));
#endif
DEBUG(errs() << "\nFunction : " << MF.getFunction()->getName() << "\n";
errs() << "<--------->\n" << MI);
int FrameIndex = MI.getOperand(i).getIndex();
int stackSize = MF.getFrameInfo()->getStackSize();
int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
#ifndef NDEBUG
DOUT << "FrameIndex : " << FrameIndex << "\n";
DOUT << "spOffset : " << spOffset << "\n";
DOUT << "stackSize : " << stackSize << "\n";
#endif
DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
<< "spOffset : " << spOffset << "\n"
<< "stackSize : " << stackSize << "\n");
// as explained on LowerFormalArguments, detect negative offsets
// and adjust SPOffsets considering the final stack size.
int Offset = ((spOffset < 0) ? (stackSize + (-(spOffset+4))) : (spOffset));
Offset += MI.getOperand(i-1).getImm();
#ifndef NDEBUG
DOUT << "Offset : " << Offset << "\n";
DOUT << "<--------->\n";
#endif
DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
MI.getOperand(i-1).ChangeToImmediate(Offset);
MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);

3
lib/Target/PowerPC/PPCHazardRecognizers.cpp
View File

@ -18,6 +18,7 @@
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
//===----------------------------------------------------------------------===//
@ -52,7 +53,7 @@ PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetInstrInfo &tii)
}
void PPCHazardRecognizer970::EndDispatchGroup() {
DOUT << "=== Start of dispatch group\n";
DEBUG(errs() << "=== Start of dispatch group\n");
NumIssued = 0;
// Structural hazard info.

81
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
View File

@ -195,7 +195,7 @@ static bool isImmZExt12(int64_t Val, int64_t &Imm) {
bool SystemZDAGToDAGISel::MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
bool is12Bit, unsigned Depth) {
DebugLoc dl = N.getDebugLoc();
DOUT << "MatchAddress: "; DEBUG(AM.dump());
DEBUG(errs() << "MatchAddress: "; AM.dump());
// Limit recursion.
if (Depth > 5)
return MatchAddressBase(N, AM);
@ -403,7 +403,7 @@ bool SystemZDAGToDAGISel::SelectAddrRI12(SDValue Op, SDValue& Addr,
if (AM12.Disp == 0 && AM20.Disp != 0)
return false;
DOUT << "MatchAddress (final): "; DEBUG(AM12.dump());
DEBUG(errs() << "MatchAddress (final): "; AM12.dump());
EVT VT = Addr.getValueType();
if (AM12.BaseType == SystemZRRIAddressMode::RegBase) {
@ -446,7 +446,7 @@ bool SystemZDAGToDAGISel::SelectAddrRI(SDValue Op, SDValue& Addr,
if (!Done && MatchAddress(Addr, AM, /* is12Bit */ false))
return false;
DOUT << "MatchAddress (final): "; DEBUG(AM.dump());
DEBUG(errs() << "MatchAddress (final): "; AM.dump());
EVT VT = Addr.getValueType();
if (AM.BaseType == SystemZRRIAddressMode::RegBase) {
@ -494,7 +494,7 @@ bool SystemZDAGToDAGISel::SelectAddrRRI12(SDValue Op, SDValue Addr,
if (AM12.Disp == 0 && AM20.Disp != 0)
return false;
DOUT << "MatchAddress (final): "; DEBUG(AM12.dump());
DEBUG(errs() << "MatchAddress (final): "; AM12.dump());
EVT VT = Addr.getValueType();
if (AM12.BaseType == SystemZRRIAddressMode::RegBase) {
@ -538,7 +538,7 @@ bool SystemZDAGToDAGISel::SelectAddrRRI20(SDValue Op, SDValue Addr,
if (!Done && MatchAddress(Addr, AM, /* is12Bit */ false))
return false;
DOUT << "MatchAddress (final): "; DEBUG(AM.dump());
DEBUG(errs() << "MatchAddress (final): "; AM.dump());
EVT VT = Addr.getValueType();
if (AM.BaseType == SystemZRRIAddressMode::RegBase) {
@ -604,14 +604,10 @@ void SystemZDAGToDAGISel::InstructionSelect() {
DEBUG(BB->dump());
// Codegen the basic block.
#ifndef NDEBUG
DOUT << "===== Instruction selection begins:\n";
DEBUG(errs() << "===== Instruction selection begins:\n");
Indent = 0;
#endif
SelectRoot(*CurDAG);
#ifndef NDEBUG
DOUT << "===== Instruction selection ends:\n";
#endif
DEBUG(errs() << "===== Instruction selection ends:\n");
CurDAG->RemoveDeadNodes();
}
@ -623,21 +619,17 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
unsigned Opcode = Node->getOpcode();
// Dump information about the Node being selected
#ifndef NDEBUG
DOUT << std::string(Indent, ' ') << "Selecting: ";
DEBUG(Node->dump(CurDAG));
DOUT << "\n";
DEBUG(errs().indent(Indent) << "Selecting: ";
Node->dump(CurDAG);
errs() << "\n");
Indent += 2;
#endif
// If we have a custom node, we already have selected!
if (Node->isMachineOpcode()) {
#ifndef NDEBUG
DOUT << std::string(Indent-2, ' ') << "== ";
DEBUG(Node->dump(CurDAG));
DOUT << "\n";
DEBUG(errs().indent(Indent-2) << "== ";
Node->dump(CurDAG);
errs() << "\n");
Indent -= 2;
#endif
return NULL; // Already selected.
}
@ -702,11 +694,9 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
MVT::i32));
ReplaceUses(Op.getValue(0), SDValue(Div, 0));
#ifndef NDEBUG
DOUT << std::string(Indent-2, ' ') << "=> ";
DEBUG(Result->dump(CurDAG));
DOUT << "\n";
#endif
DEBUG(errs().indent(Indent-2) << "=> ";
Result->dump(CurDAG);
errs() << "\n");
}
// Copy the remainder (even subreg) result, if it is needed.
@ -719,11 +709,9 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
MVT::i32));
ReplaceUses(Op.getValue(1), SDValue(Rem, 0));
#ifndef NDEBUG
DOUT << std::string(Indent-2, ' ') << "=> ";
DEBUG(Result->dump(CurDAG));
DOUT << "\n";
#endif
DEBUG(errs().indent(Indent-2) << "=> ";
Result->dump(CurDAG);
errs() << "\n");
}
#ifndef NDEBUG
@ -795,11 +783,9 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
CurDAG->getTargetConstant(SubRegIdx,
MVT::i32));
ReplaceUses(Op.getValue(0), SDValue(Div, 0));
#ifndef NDEBUG
DOUT << std::string(Indent-2, ' ') << "=> ";
DEBUG(Result->dump(CurDAG));
DOUT << "\n";
#endif
DEBUG(errs().indent(Indent-2) << "=> ";
Result->dump(CurDAG);
errs() << "\n");
}
// Copy the remainder (even subreg) result, if it is needed.
@ -811,11 +797,9 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
CurDAG->getTargetConstant(SubRegIdx,
MVT::i32));
ReplaceUses(Op.getValue(1), SDValue(Rem, 0));
#ifndef NDEBUG
DOUT << std::string(Indent-2, ' ') << "=> ";
DEBUG(Result->dump(CurDAG));
DOUT << "\n";
#endif
DEBUG(errs().indent(Indent-2) << "=> ";
Result->dump(CurDAG);
errs() << "\n");
}
#ifndef NDEBUG
@ -829,15 +813,14 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
// Select the default instruction
SDNode *ResNode = SelectCode(Op);
#ifndef NDEBUG
DOUT << std::string(Indent-2, ' ') << "=> ";
if (ResNode == NULL || ResNode == Op.getNode())
DEBUG(Op.getNode()->dump(CurDAG));
else
DEBUG(ResNode->dump(CurDAG));
DOUT << "\n";
DEBUG(errs().indent(Indent-2) << "=> ";
if (ResNode == NULL || ResNode == Op.getNode())
Op.getNode()->dump(CurDAG);
else
ResNode->dump(CurDAG);
errs() << "\n";
);
Indent -= 2;
#endif
return ResNode;
}

5
lib/Target/XCore/XCoreRegisterInfo.cpp
View File

@ -208,10 +208,7 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
assert(Offset%4 == 0 && "Misaligned stack offset");
#ifndef NDEBUG
DOUT << "Offset : " << Offset << "\n";
DOUT << "<--------->\n";
#endif
DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
Offset/=4;