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[x86] enable machine combiner reassociations for 256-bit vector logical integer insts

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llvm-svn: 248955
This commit is contained in:
Sanjay Patel 2015-09-30 22:25:55 +00:00
parent 8474784569
commit 275d6f22b1
2 changed files with 49 additions and 2 deletions
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3
lib/Target/X86/X86InstrInfo.cpp
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@ -6373,8 +6373,11 @@ bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
case X86::PORrr:
case X86::PXORrr:
case X86::VPANDrr:
case X86::VPANDYrr:
case X86::VPORrr:
case X86::VPORYrr:
case X86::VPXORrr:
case X86::VPXORYrr:
// Normal min/max instructions are not commutative because of NaN and signed
// zero semantics, but these are. Thus, there's no need to check for global
// relaxed math; the instructions themselves have the properties we need.

48
test/CodeGen/X86/machine-combiner-int-vec.ll
View File

@ -1,5 +1,5 @@
; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=sse < %s | FileCheck %s --check-prefix=SSE
; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=avx < %s | FileCheck %s --check-prefix=AVX
; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=sse2 < %s | FileCheck %s --check-prefix=SSE
; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=avx2 < %s | FileCheck %s --check-prefix=AVX
; Verify that 128-bit vector logical ops are reassociated.
@ -66,3 +66,47 @@ define <4 x i32> @reassociate_xor_v4i32(<4 x i32> %x0, <4 x i32> %x1, <4 x i32>
ret <4 x i32> %t2
}
; Verify that 256-bit vector logical ops are reassociated.
define <8 x i32> @reassociate_and_v8i32(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, <8 x i32> %x3) {
; AVX-LABEL: reassociate_and_v8i32:
; AVX: # BB#0:
; AVX-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; AVX-NEXT: vpand %ymm3, %ymm2, %ymm1
; AVX-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX-NEXT: retq
%t0 = add <8 x i32> %x0, %x1
%t1 = and <8 x i32> %x2, %t0
%t2 = and <8 x i32> %x3, %t1
ret <8 x i32> %t2
}
define <8 x i32> @reassociate_or_v8i32(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, <8 x i32> %x3) {
; AVX-LABEL: reassociate_or_v8i32:
; AVX: # BB#0:
; AVX-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; AVX-NEXT: vpor %ymm3, %ymm2, %ymm1
; AVX-NEXT: vpor %ymm1, %ymm0, %ymm0
; AVX-NEXT: retq
%t0 = add <8 x i32> %x0, %x1
%t1 = or <8 x i32> %x2, %t0
%t2 = or <8 x i32> %x3, %t1
ret <8 x i32> %t2
}
define <8 x i32> @reassociate_xor_v8i32(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, <8 x i32> %x3) {
; AVX-LABEL: reassociate_xor_v8i32:
; AVX: # BB#0:
; AVX-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; AVX-NEXT: vpxor %ymm3, %ymm2, %ymm1
; AVX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; AVX-NEXT: retq
%t0 = add <8 x i32> %x0, %x1
%t1 = xor <8 x i32> %x2, %t0
%t2 = xor <8 x i32> %x3, %t1
ret <8 x i32> %t2
}