Special constants as destinations does not work as expected - drop the patterns.

llvm-svn: 78191
This commit is contained in:
Anton Korobeynikov 2009-08-05 14:42:00 +00:00
parent 1c03c3e158
commit 27fdf43425

View File

@ -722,59 +722,6 @@ def CMP16im : Pseudo<(outs), (ins i16imm:$src1, memsrc:$src2),
"cmp.w\t{$src1, $src2}",
[(MSP430cmp (i16 imm:$src1), (load addr:$src2)), (implicit SRW)]>;
// FIXME: imm is allowed only on src operand, not on dst.
//def CMP8ri : Pseudo<(outs), (ins GR8:$src1, i8imm:$src2),
// "cmp.b\t{$src1, $src2}",
// [(MSP430cmp GR8:$src1, imm:$src2), (implicit SRW)]>;
//def CMP16ri : Pseudo<(outs), (ins GR16:$src1, i16imm:$src2),
// "cmp.w\t{$src1, $src2}",
// [(MSP430cmp GR16:$src1, imm:$src2), (implicit SRW)]>;
//def CMP8mi : Pseudo<(outs), (ins memsrc:$src1, i8imm:$src2),
// "cmp.b\t{$src1, $src2}",
// [(MSP430cmp (load addr:$src1), (i8 imm:$src2)), (implicit SRW)]>;
//def CMP16mi : Pseudo<(outs), (ins memsrc:$src1, i16imm:$src2),
// "cmp.w\t{$src1, $src2}",
// [(MSP430cmp (load addr:$src1), (i16 imm:$src2)), (implicit SRW)]>;
// Imm 0, +1, +2, +4, +8 are encoded via constant generator registers.
// That's why we can use them as dest operands.
// We don't define new class for them, since they would need special encoding
// in the future.
def CMP8ri0 : Pseudo<(outs), (ins GR8:$src1),
"cmp.b\t{$src1, #0}",
[(MSP430cmp GR8:$src1, 0), (implicit SRW)]>;
def CMP16ri0: Pseudo<(outs), (ins GR16:$src1),
"cmp.w\t{$src1, #0}",
[(MSP430cmp GR16:$src1, 0), (implicit SRW)]>;
def CMP8ri1 : Pseudo<(outs), (ins GR8:$src1),
"cmp.b\t{$src1, #1}",
[(MSP430cmp GR8:$src1, 1), (implicit SRW)]>;
def CMP16ri1: Pseudo<(outs), (ins GR16:$src1),
"cmp.w\t{$src1, #1}",
[(MSP430cmp GR16:$src1, 1), (implicit SRW)]>;
def CMP8ri2 : Pseudo<(outs), (ins GR8:$src1),
"cmp.b\t{$src1, #2}",
[(MSP430cmp GR8:$src1, 2), (implicit SRW)]>;
def CMP16ri2: Pseudo<(outs), (ins GR16:$src1),
"cmp.w\t{$src1, #2}",
[(MSP430cmp GR16:$src1, 2), (implicit SRW)]>;
def CMP8ri4 : Pseudo<(outs), (ins GR8:$src1),
"cmp.b\t{$src1, #4}",
[(MSP430cmp GR8:$src1, 4), (implicit SRW)]>;
def CMP16ri4: Pseudo<(outs), (ins GR16:$src1),
"cmp.w\t{$src1, #4}",
[(MSP430cmp GR16:$src1, 4), (implicit SRW)]>;
def CMP8ri8 : Pseudo<(outs), (ins GR8:$src1),
"cmp.b\t{$src1, #8}",
[(MSP430cmp GR8:$src1, 8), (implicit SRW)]>;
def CMP16ri8: Pseudo<(outs), (ins GR16:$src1),
"cmp.w\t{$src1, #8}",
[(MSP430cmp GR16:$src1, 8), (implicit SRW)]>;
def CMP8rm : Pseudo<(outs), (ins GR8:$src1, memsrc:$src2),
"cmp.b\t{$src1, $src2}",
[(MSP430cmp GR8:$src1, (load addr:$src2)), (implicit SRW)]>;