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Apply clang-tidy's misc-static-assert where it makes sense.

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Also fold conditions into assert(0) where it makes sense. No functional
change intended.

llvm-svn: 270982
This commit is contained in:
Benjamin Kramer 2016-05-27 11:36:04 +00:00
parent 5a2861b1b6
commit 284d6ac8f3
8 changed files with 32 additions and 33 deletions
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10
lib/CodeGen/DFAPacketizer.cpp
View File

@ -60,10 +60,12 @@ DFAPacketizer::DFAPacketizer(const InstrItineraryData *I,
InstrItins(I), CurrentState(0), DFAStateInputTable(SIT),
DFAStateEntryTable(SET) {
// Make sure DFA types are large enough for the number of terms & resources.
assert((DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <= (8 * sizeof(DFAInput))
&& "(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for DFAInput");
assert((DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <= (8 * sizeof(DFAStateInput))
&& "(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for DFAStateInput");
static_assert((DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <=
(8 * sizeof(DFAInput)),
"(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for DFAInput");
static_assert(
(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <= (8 * sizeof(DFAStateInput)),
"(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for DFAStateInput");
}

8
lib/Target/AArch64/AArch64FastISel.cpp
View File

@ -1607,8 +1607,8 @@ unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT,
unsigned LHSReg, bool LHSIsKill,
uint64_t Imm) {
assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR) &&
"ISD nodes are not consecutive!");
static_assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR),
"ISD nodes are not consecutive!");
static const unsigned OpcTable[3][2] = {
{ AArch64::ANDWri, AArch64::ANDXri },
{ AArch64::ORRWri, AArch64::ORRXri },
@ -1654,8 +1654,8 @@ unsigned AArch64FastISel::emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT,
unsigned LHSReg, bool LHSIsKill,
unsigned RHSReg, bool RHSIsKill,
uint64_t ShiftImm) {
assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR) &&
"ISD nodes are not consecutive!");
static_assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR),
"ISD nodes are not consecutive!");
static const unsigned OpcTable[3][2] = {
{ AArch64::ANDWrs, AArch64::ANDXrs },
{ AArch64::ORRWrs, AArch64::ORRXrs },

8
lib/Target/AArch64/AArch64InstrInfo.cpp
View File

@ -1447,8 +1447,8 @@ bool AArch64InstrInfo::isScaledAddr(const MachineInstr *MI) const {
/// Check all MachineMemOperands for a hint to suppress pairing.
bool AArch64InstrInfo::isLdStPairSuppressed(const MachineInstr *MI) const {
assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits) &&
"Too many target MO flags");
static_assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits),
"Too many target MO flags");
for (auto *MM : MI->memoperands()) {
if (MM->getFlags() &
(MOSuppressPair << MachineMemOperand::MOTargetStartBit)) {
@ -1463,8 +1463,8 @@ void AArch64InstrInfo::suppressLdStPair(MachineInstr *MI) const {
if (MI->memoperands_empty())
return;
assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits) &&
"Too many target MO flags");
static_assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits),
"Too many target MO flags");
(*MI->memoperands_begin())
->setFlags(MOSuppressPair << MachineMemOperand::MOTargetStartBit);
}

18
lib/Target/AMDGPU/SIMachineScheduler.cpp
View File

@ -522,12 +522,9 @@ void SIScheduleBlock::addPred(SIScheduleBlock *Pred) {
}
Preds.push_back(Pred);
#ifndef NDEBUG
for (SIScheduleBlock* S : Succs) {
if (PredID == S->getID())
assert(!"Loop in the Block Graph!\n");
}
#endif
assert(none_of(Succs,
[=](SIScheduleBlock *S) { return PredID == S->getID(); }) &&
"Loop in the Block Graph!");
}
void SIScheduleBlock::addSucc(SIScheduleBlock *Succ) {
@ -541,12 +538,9 @@ void SIScheduleBlock::addSucc(SIScheduleBlock *Succ) {
if (Succ->isHighLatencyBlock())
++NumHighLatencySuccessors;
Succs.push_back(Succ);
#ifndef NDEBUG
for (SIScheduleBlock* P : Preds) {
if (SuccID == P->getID())
assert(!"Loop in the Block Graph!\n");
}
#endif
assert(none_of(Preds,
[=](SIScheduleBlock *P) { return SuccID == P->getID(); }) &&
"Loop in the Block Graph!");
}
#ifndef NDEBUG

12
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -1936,8 +1936,9 @@ void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
// Extract out the subregisters.
SDValue SuperReg = SDValue(VLd, 0);
assert(ARM::dsub_7 == ARM::dsub_0+7 &&
ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
static_assert(ARM::dsub_7 == ARM::dsub_0 + 7 &&
ARM::qsub_3 == ARM::qsub_0 + 3,
"Unexpected subreg numbering");
unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
ReplaceUses(SDValue(N, Vec),
@ -2205,8 +2206,9 @@ void ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad, bool isUpdating,
// Extract the subregisters.
SuperReg = SDValue(VLdLn, 0);
assert(ARM::dsub_7 == ARM::dsub_0+7 &&
ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
static_assert(ARM::dsub_7 == ARM::dsub_0 + 7 &&
ARM::qsub_3 == ARM::qsub_0 + 3,
"Unexpected subreg numbering");
unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
ReplaceUses(SDValue(N, Vec),
@ -2288,7 +2290,7 @@ void ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
SuperReg = SDValue(VLdDup, 0);
// Extract the subregisters.
assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
static_assert(ARM::dsub_7 == ARM::dsub_0 + 7, "Unexpected subreg numbering");
unsigned SubIdx = ARM::dsub_0;
for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
ReplaceUses(SDValue(N, Vec),

4
lib/Target/Hexagon/HexagonFrameLowering.cpp
View File

@ -222,8 +222,8 @@ namespace {
/// Returns the callee saved register with the largest id in the vector.
unsigned getMaxCalleeSavedReg(const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo &TRI) {
assert(Hexagon::R1 > 0 &&
"Assume physical registers are encoded as positive integers");
static_assert(Hexagon::R1 > 0,
"Assume physical registers are encoded as positive integers");
if (CSI.empty())
return 0;

2
lib/Target/Hexagon/HexagonGenPredicate.cpp
View File

@ -155,7 +155,7 @@ unsigned HexagonGenPredicate::getPredForm(unsigned Opc) {
// The opcode corresponding to 0 is TargetOpcode::PHI. We can use 0 here
// to denote "none", but we need to make sure that none of the valid opcodes
// that we return will ever be 0.
assert(PHI == 0 && "Use different value for <none>");
static_assert(PHI == 0, "Use different value for <none>");
return 0;
}

3
lib/Target/Sparc/SparcISelLowering.cpp
View File

@ -185,7 +185,8 @@ static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT,
// callee's register window. This function translates registers to the
// corresponding caller window %o register.
static unsigned toCallerWindow(unsigned Reg) {
assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum");
static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7,
"Unexpected enum");
if (Reg >= SP::I0 && Reg <= SP::I7)
return Reg - SP::I0 + SP::O0;
return Reg;