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Pass a Banner argument to the machine code verifier both from
createMachineVerifierPass and MachineFunction::verify. The banner is printed before the machine code dump, just like the printer pass. llvm-svn: 122113
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@ -271,7 +271,7 @@ public:
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/// verify - Run the current MachineFunction through the machine code
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/// verifier, useful for debugger use.
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void verify(Pass *p=NULL) const;
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void verify(Pass *p = NULL, const char *Banner = NULL) const;
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// Provide accessors for the MachineBasicBlock list...
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typedef BasicBlockListType::iterator iterator;
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@ -206,7 +206,7 @@ namespace llvm {
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/// createMachineVerifierPass - This pass verifies cenerated machine code
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/// instructions for correctness.
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FunctionPass *createMachineVerifierPass();
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FunctionPass *createMachineVerifierPass(const char *Banner = 0);
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/// createDwarfEHPass - This pass mulches exception handling code into a form
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/// adapted to code generation. Required if using dwarf exception handling.
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@ -96,7 +96,7 @@ Spiller *createInlineSpiller(MachineFunctionPass &pass,
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MachineFunction &mf,
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VirtRegMap &vrm) {
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if (VerifySpills)
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mf.verify(&pass);
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mf.verify(&pass, "When creating inline spiller");
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return new InlineSpiller(pass, mf, vrm);
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}
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}
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@ -313,7 +313,7 @@ void InlineSpiller::spill(LiveInterval *li,
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LiveRangeEdit edit(*li, newIntervals, spillIs);
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spill(edit);
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if (VerifySpills)
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mf_.verify(&pass_);
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mf_.verify(&pass_, "After inline spill");
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}
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void InlineSpiller::spill(LiveRangeEdit &edit) {
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@ -251,7 +251,7 @@ static void printAndVerify(PassManagerBase &PM,
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PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
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if (VerifyMachineCode)
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PM.add(createMachineVerifierPass());
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PM.add(createMachineVerifierPass(Banner));
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}
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/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
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@ -46,14 +46,16 @@ using namespace llvm;
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namespace {
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struct MachineVerifier {
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MachineVerifier(Pass *pass) :
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MachineVerifier(Pass *pass, const char *b) :
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PASS(pass),
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Banner(b),
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OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
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{}
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bool runOnMachineFunction(MachineFunction &MF);
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Pass *const PASS;
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const char *Banner;
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const char *const OutFileName;
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raw_ostream *OS;
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const MachineFunction *MF;
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@ -196,9 +198,10 @@ namespace {
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struct MachineVerifierPass : public MachineFunctionPass {
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static char ID; // Pass ID, replacement for typeid
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const char *const Banner;
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MachineVerifierPass()
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: MachineFunctionPass(ID) {
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MachineVerifierPass(const char *b = 0)
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: MachineFunctionPass(ID), Banner(b) {
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initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
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}
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@ -208,7 +211,7 @@ namespace {
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}
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bool runOnMachineFunction(MachineFunction &MF) {
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MF.verify(this);
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MF.verify(this, Banner);
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return false;
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}
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};
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@ -219,12 +222,13 @@ char MachineVerifierPass::ID = 0;
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INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
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"Verify generated machine code", false, false)
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FunctionPass *llvm::createMachineVerifierPass() {
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return new MachineVerifierPass();
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FunctionPass *llvm::createMachineVerifierPass(const char *Banner) {
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return new MachineVerifierPass(Banner);
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}
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void MachineFunction::verify(Pass *p) const {
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MachineVerifier(p).runOnMachineFunction(const_cast<MachineFunction&>(*this));
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void MachineFunction::verify(Pass *p, const char *Banner) const {
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MachineVerifier(p, Banner)
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.runOnMachineFunction(const_cast<MachineFunction&>(*this));
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}
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bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
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@ -297,8 +301,11 @@ bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
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void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
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assert(MF);
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*OS << '\n';
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if (!foundErrors++)
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if (!foundErrors++) {
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if (Banner)
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*OS << "# " << Banner << '\n';
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MF->print(*OS, Indexes);
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}
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*OS << "*** Bad machine code: " << msg << " ***\n"
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<< "- function: " << MF->getFunction()->getNameStr() << "\n";
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}
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@ -484,7 +484,7 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) {
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// spiller. Always use -spiller=inline with -verify-regalloc. Even with the
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// inline spiller, some tests fail to verify because the coalescer does not
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// always generate verifiable code.
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MF->verify(this);
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MF->verify(this, "In RABasic::verify");
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// Verify that LiveIntervals are partitioned into unions and disjoint within
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// the unions.
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@ -329,7 +329,7 @@ unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
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.splitAroundLoop(Loop->getLoop());
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if (VerifyEnabled)
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MF->verify(this);
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MF->verify(this, "After splitting live range around loop");
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// We have new split regs, don't assign anything.
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return 0;
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@ -404,7 +404,7 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
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MF = &mf;
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if (VerifyEnabled)
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MF->verify(this);
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MF->verify(this, "Before greedy register allocator");
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RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
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DomTree = &getAnalysis<MachineDominatorTree>();
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