mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-01-10 22:00:58 +00:00
[mips][microMIPSr6] Implement initial mapping support
Differential Revision: http://reviews.llvm.org/D8387 llvm-svn: 235298
This commit is contained in:
parent
31831db8f5
commit
28864478e6
@ -179,8 +179,10 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
(Opcode != Mips::SLL_MM) && !Binary)
|
||||
llvm_unreachable("unimplemented opcode in EncodeInstruction()");
|
||||
|
||||
if (STI.getFeatureBits() & Mips::FeatureMicroMips) {
|
||||
int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips);
|
||||
if (isMicroMips(STI)) {
|
||||
int NewOpcode = isMips32r6(STI) ?
|
||||
Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6) :
|
||||
Mips::Std2MicroMips(Opcode, Mips::Arch_micromips);
|
||||
if (NewOpcode != -1) {
|
||||
if (Fixups.size() > N)
|
||||
Fixups.pop_back();
|
||||
|
17
lib/Target/Mips/MicroMips32r6InstrFormats.td
Normal file
17
lib/Target/Mips/MicroMips32r6InstrFormats.td
Normal file
@ -0,0 +1,17 @@
|
||||
//=- MicroMips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file describes microMIPS32r6 instruction formats.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class MMR6Arch<string opstr> {
|
||||
string Arch = "micromipsr6";
|
||||
string BaseOpcode = opstr;
|
||||
}
|
@ -11,6 +11,25 @@
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class R6MMR6Rel;
|
||||
|
||||
def MipsR62MicroMipsR6 : InstrMapping {
|
||||
let FilterClass = "R6MMR6Rel";
|
||||
// Instructions with the same BaseOpcode and isNVStore values form a row.
|
||||
let RowFields = ["BaseOpcode"];
|
||||
// Instructions with the same predicate sense form a column.
|
||||
let ColFields = ["Arch"];
|
||||
// The key column is the unpredicated instructions.
|
||||
let KeyCol = ["mipsr6"];
|
||||
// Value columns are PredSense=true and PredSense=false
|
||||
let ValueCols = [["mipsr6"], ["micromipsr6"]];
|
||||
}
|
||||
|
||||
class MipsR6Arch<string opstr> {
|
||||
string Arch = "mipsr6";
|
||||
string BaseOpcode = opstr;
|
||||
}
|
||||
|
||||
class MipsR6Inst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>,
|
||||
PredicateControl {
|
||||
let DecoderNamespace = "Mips32r6_64r6";
|
||||
|
Loading…
x
Reference in New Issue
Block a user