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AMDGPU: Match some med3 patterns
llvm-svn: 259089
This commit is contained in:
Matt Arsenault
parent
2c5f486332
commit
28a667546a
@ -169,6 +169,12 @@ def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
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[FeatureFP64]
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>;
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def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
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"FPExceptions",
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"true",
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"Enable floating point exceptions"
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>;
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def FeatureEnableHugeScratchBuffer : SubtargetFeature<
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"huge-scratch-buffer",
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"EnableHugeScratchBuffer",
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@ -397,7 +397,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM,
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// SI at least has hardware support for floating point exceptions, but no way
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// of using or handling them is implemented. They are also optional in OpenCL
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// (Section 7.3)
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setHasFloatingPointExceptions(false);
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setHasFloatingPointExceptions(Subtarget->hasFPExceptions());
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setSelectIsExpensive(false);
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PredictableSelectIsExpensive = false;
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@ -2949,6 +2949,9 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
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NODE_NAME_CASE(FMIN3)
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NODE_NAME_CASE(SMIN3)
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NODE_NAME_CASE(UMIN3)
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NODE_NAME_CASE(FMED3)
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NODE_NAME_CASE(SMED3)
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NODE_NAME_CASE(UMED3)
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NODE_NAME_CASE(URECIP)
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NODE_NAME_CASE(DIV_SCALE)
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NODE_NAME_CASE(DIV_FMAS)
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@ -257,6 +257,9 @@ enum NodeType : unsigned {
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FMIN3,
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SMIN3,
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UMIN3,
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FMED3,
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SMED3,
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UMED3,
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URECIP,
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DIV_SCALE,
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DIV_FMAS,
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@ -209,6 +209,16 @@ def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp,
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[]
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>;
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def AMDGPUsmed3 : SDNode<"AMDGPUISD::SMED3", AMDGPUDTIntTernaryOp,
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[]
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>;
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def AMDGPUumed3 : SDNode<"AMDGPUISD::UMED3", AMDGPUDTIntTernaryOp,
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[]
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>;
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def AMDGPUfmed3 : SDNode<"AMDGPUISD::FMED3", SDTFPTernaryOp, []>;
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def AMDGPUsendmsg : SDNode<"AMDGPUISD::SENDMSG",
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SDTypeProfile<0, 1, [SDTCisInt<0>]>,
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[SDNPHasChain, SDNPInGlue]>;
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@ -66,9 +66,9 @@ AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
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: AMDGPUGenSubtargetInfo(TT, GPU, FS),
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DumpCode(false), R600ALUInst(false), HasVertexCache(false),
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TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
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FP64Denormals(false), FP32Denormals(false), FastFMAF32(false),
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HalfRate64Ops(false), CaymanISA(false), FlatAddressSpace(false),
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FlatForGlobal(false), EnableIRStructurizer(true),
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FP64Denormals(false), FP32Denormals(false), FPExceptions(false),
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FastFMAF32(false), HalfRate64Ops(false), CaymanISA(false),
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FlatAddressSpace(false), FlatForGlobal(false), EnableIRStructurizer(true),
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EnablePromoteAlloca(false),
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EnableIfCvt(true), EnableLoadStoreOpt(false),
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EnableUnsafeDSOffsetFolding(false),
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@ -66,6 +66,7 @@ private:
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bool FP64;
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bool FP64Denormals;
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bool FP32Denormals;
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bool FPExceptions;
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bool FastFMAF32;
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bool HalfRate64Ops;
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bool CaymanISA;
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@ -150,6 +151,10 @@ public:
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return FP64Denormals;
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}
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bool hasFPExceptions() const {
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return FPExceptions;
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}
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bool hasFastFMAF32() const {
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return FastFMAF32;
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}
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@ -2131,8 +2131,70 @@ static unsigned minMaxOpcToMin3Max3Opc(unsigned Opc) {
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}
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}
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SDValue SITargetLowering::performMin3Max3Combine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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static SDValue performIntMed3ImmCombine(SelectionDAG &DAG,
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SDLoc SL,
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SDValue Op0,
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SDValue Op1,
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bool Signed) {
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ConstantSDNode *K1 = dyn_cast<ConstantSDNode>(Op1);
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if (!K1)
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return SDValue();
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ConstantSDNode *K0 = dyn_cast<ConstantSDNode>(Op0.getOperand(1));
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if (!K0)
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return SDValue();
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if (Signed) {
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if (K0->getAPIntValue().sge(K1->getAPIntValue()))
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return SDValue();
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} else {
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if (K0->getAPIntValue().uge(K1->getAPIntValue()))
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return SDValue();
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}
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EVT VT = K0->getValueType(0);
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return DAG.getNode(Signed ? AMDGPUISD::SMED3 : AMDGPUISD::UMED3, SL, VT,
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Op0.getOperand(0), SDValue(K0, 0), SDValue(K1, 0));
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}
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static bool isKnownNeverSNan(SelectionDAG &DAG, SDValue Op) {
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if (!DAG.getTargetLoweringInfo().hasFloatingPointExceptions())
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return true;
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return DAG.isKnownNeverNaN(Op);
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}
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static SDValue performFPMed3ImmCombine(SelectionDAG &DAG,
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SDLoc SL,
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SDValue Op0,
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SDValue Op1) {
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ConstantFPSDNode *K1 = dyn_cast<ConstantFPSDNode>(Op1);
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if (!K1)
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return SDValue();
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ConstantFPSDNode *K0 = dyn_cast<ConstantFPSDNode>(Op0.getOperand(1));
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if (!K0)
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return SDValue();
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// Ordered >= (although NaN inputs should have folded away by now).
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APFloat::cmpResult Cmp = K0->getValueAPF().compare(K1->getValueAPF());
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if (Cmp == APFloat::cmpGreaterThan)
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return SDValue();
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// This isn't safe with signaling NaNs because in IEEE mode, min/max on a
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// signaling NaN gives a quiet NaN. The quiet NaN input to the min would then
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// give the other result, which is different from med3 with a NaN input.
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SDValue Var = Op0.getOperand(0);
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if (!isKnownNeverSNan(DAG, Var))
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return SDValue();
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return DAG.getNode(AMDGPUISD::FMED3, SL, K0->getValueType(0),
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Var, SDValue(K0, 0), SDValue(K1, 0));
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}
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SDValue SITargetLowering::performMinMaxCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
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unsigned Opc = N->getOpcode();
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@ -2142,7 +2204,8 @@ SDValue SITargetLowering::performMin3Max3Combine(SDNode *N,
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// Only do this if the inner op has one use since this will just increases
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// register pressure for no benefit.
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// max(max(a, b), c)
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// max(max(a, b), c) -> max3(a, b, c)
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// min(min(a, b), c) -> min3(a, b, c)
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if (Op0.getOpcode() == Opc && Op0.hasOneUse()) {
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SDLoc DL(N);
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return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
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@ -2153,7 +2216,9 @@ SDValue SITargetLowering::performMin3Max3Combine(SDNode *N,
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Op1);
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}
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// max(a, max(b, c))
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// Try commuted.
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// max(a, max(b, c)) -> max3(a, b, c)
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// min(a, min(b, c)) -> min3(a, b, c)
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if (Op1.getOpcode() == Opc && Op1.hasOneUse()) {
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SDLoc DL(N);
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return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
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@ -2164,6 +2229,24 @@ SDValue SITargetLowering::performMin3Max3Combine(SDNode *N,
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Op1.getOperand(1));
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}
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// min(max(x, K0), K1), K0 < K1 -> med3(x, K0, K1)
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if (Opc == ISD::SMIN && Op0.getOpcode() == ISD::SMAX && Op0.hasOneUse()) {
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if (SDValue Med3 = performIntMed3ImmCombine(DAG, SDLoc(N), Op0, Op1, true))
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return Med3;
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}
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if (Opc == ISD::UMIN && Op0.getOpcode() == ISD::UMAX && Op0.hasOneUse()) {
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if (SDValue Med3 = performIntMed3ImmCombine(DAG, SDLoc(N), Op0, Op1, false))
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return Med3;
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}
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// fminnum(fmaxnum(x, K0), K1), K0 < K1 && !is_snan(x) -> fmed3(x, K0, K1)
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if (Opc == ISD::FMINNUM && Op0.getOpcode() == ISD::FMAXNUM &&
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N->getValueType(0) == MVT::f32 && Op0.hasOneUse()) {
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if (SDValue Res = performFPMed3ImmCombine(DAG, SDLoc(N), Op0, Op1))
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return Res;
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}
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return SDValue();
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}
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@ -2217,7 +2300,7 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
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if (DCI.getDAGCombineLevel() >= AfterLegalizeDAG &&
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N->getValueType(0) != MVT::f64 &&
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getTargetMachine().getOptLevel() > CodeGenOpt::None)
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return performMin3Max3Combine(N, DCI);
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return performMinMaxCombine(N, DCI);
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break;
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}
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@ -54,7 +54,8 @@ class SITargetLowering : public AMDGPUTargetLowering {
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SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performMin3Max3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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bool isLegalFlatAddressingMode(const AddrMode &AM) const;
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@ -1695,13 +1695,13 @@ defm V_MAX3_U32 : VOP3Inst <vop3<0x156, 0x1d5>, "v_max3_u32",
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VOP_I32_I32_I32_I32, AMDGPUumax3
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>;
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defm V_MED3_F32 : VOP3Inst <vop3<0x157, 0x1d6>, "v_med3_f32",
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VOP_F32_F32_F32_F32
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VOP_F32_F32_F32_F32, AMDGPUfmed3
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>;
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defm V_MED3_I32 : VOP3Inst <vop3<0x158, 0x1d7>, "v_med3_i32",
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VOP_I32_I32_I32_I32
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VOP_I32_I32_I32_I32, AMDGPUsmed3
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>;
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defm V_MED3_U32 : VOP3Inst <vop3<0x159, 0x1d8>, "v_med3_u32",
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VOP_I32_I32_I32_I32
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VOP_I32_I32_I32_I32, AMDGPUumed3
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>;
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//def V_SAD_U8 : VOP3_U8 <0x0000015a, "v_sad_u8", []>;
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131
test/CodeGen/AMDGPU/fmed3.ll
Normal file
131
test/CodeGen/AMDGPU/fmed3.ll
Normal file
@ -0,0 +1,131 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=NOSNAN -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mattr=+fp-exceptions -verify-machineinstrs < %s | FileCheck -check-prefix=SNAN -check-prefix=GCN %s
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declare i32 @llvm.r600.read.tidig.x() #0
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declare float @llvm.minnum.f32(float, float) #0
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declare float @llvm.maxnum.f32(float, float) #0
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declare double @llvm.minnum.f64(double, double) #0
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declare double @llvm.maxnum.f64(double, double) #0
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; GCN-LABEL: {{^}}v_test_fmed3_r_i_i_f32:
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; NOSNAN: v_med3_f32 v{{[0-9]+}}, v{{[0-9]+}}, 2.0, 4.0
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; SNAN: v_max_f32_e32 v{{[0-9]+}}, 2.0, v{{[0-9]+}}
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; SNAN: v_min_f32_e32 v{{[0-9]+}}, 4.0, v{{[0-9]+}}
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define void @v_test_fmed3_r_i_i_f32(float addrspace(1)* %out, float addrspace(1)* %aptr) #1 {
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%tid = call i32 @llvm.r600.read.tidig.x()
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%gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid
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%outgep = getelementptr float, float addrspace(1)* %out, i32 %tid
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%a = load float, float addrspace(1)* %gep0
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%max = call float @llvm.maxnum.f32(float %a, float 2.0)
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%med = call float @llvm.minnum.f32(float %max, float 4.0)
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store float %med, float addrspace(1)* %outgep
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ret void
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}
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; GCN-LABEL: {{^}}v_test_fmed3_r_i_i_commute0_f32:
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; NOSNAN: v_med3_f32 v{{[0-9]+}}, v{{[0-9]+}}, 2.0, 4.0
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; SNAN: v_max_f32_e32 v{{[0-9]+}}, 2.0, v{{[0-9]+}}
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; SNAN: v_min_f32_e32 v{{[0-9]+}}, 4.0, v{{[0-9]+}}
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define void @v_test_fmed3_r_i_i_commute0_f32(float addrspace(1)* %out, float addrspace(1)* %aptr) #1 {
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%tid = call i32 @llvm.r600.read.tidig.x()
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%gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid
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%outgep = getelementptr float, float addrspace(1)* %out, i32 %tid
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%a = load float, float addrspace(1)* %gep0
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%max = call float @llvm.maxnum.f32(float 2.0, float %a)
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%med = call float @llvm.minnum.f32(float 4.0, float %max)
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store float %med, float addrspace(1)* %outgep
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ret void
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}
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; GCN-LABEL: {{^}}v_test_fmed3_r_i_i_commute1_f32:
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; NOSNAN: v_med3_f32 v{{[0-9]+}}, v{{[0-9]+}}, 2.0, 4.0
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; SNAN: v_max_f32_e32 v{{[0-9]+}}, 2.0, v{{[0-9]+}}
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; SNAN: v_min_f32_e32 v{{[0-9]+}}, 4.0, v{{[0-9]+}}
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define void @v_test_fmed3_r_i_i_commute1_f32(float addrspace(1)* %out, float addrspace(1)* %aptr) #1 {
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%tid = call i32 @llvm.r600.read.tidig.x()
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%gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid
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%outgep = getelementptr float, float addrspace(1)* %out, i32 %tid
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%a = load float, float addrspace(1)* %gep0
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%max = call float @llvm.maxnum.f32(float %a, float 2.0)
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%med = call float @llvm.minnum.f32(float 4.0, float %max)
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store float %med, float addrspace(1)* %outgep
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ret void
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}
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; GCN-LABEL: {{^}}v_test_fmed3_r_i_i_constant_order_f32:
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; GCN: v_max_f32_e32 v{{[0-9]+}}, 4.0, v{{[0-9]+}}
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; GCN: v_min_f32_e32 v{{[0-9]+}}, 2.0, v{{[0-9]+}}
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define void @v_test_fmed3_r_i_i_constant_order_f32(float addrspace(1)* %out, float addrspace(1)* %aptr) #1 {
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%tid = call i32 @llvm.r600.read.tidig.x()
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%gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid
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%outgep = getelementptr float, float addrspace(1)* %out, i32 %tid
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%a = load float, float addrspace(1)* %gep0
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%max = call float @llvm.maxnum.f32(float %a, float 4.0)
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%med = call float @llvm.minnum.f32(float %max, float 2.0)
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store float %med, float addrspace(1)* %outgep
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ret void
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}
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; GCN-LABEL: {{^}}v_test_fmed3_r_i_i_multi_use_f32:
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; GCN: v_max_f32_e32 v{{[0-9]+}}, 2.0, v{{[0-9]+}}
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; GCN: v_min_f32_e32 v{{[0-9]+}}, 4.0, v{{[0-9]+}}
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define void @v_test_fmed3_r_i_i_multi_use_f32(float addrspace(1)* %out, float addrspace(1)* %aptr) #1 {
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%tid = call i32 @llvm.r600.read.tidig.x()
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%gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid
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%outgep = getelementptr float, float addrspace(1)* %out, i32 %tid
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%a = load float, float addrspace(1)* %gep0
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%max = call float @llvm.maxnum.f32(float %a, float 2.0)
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%med = call float @llvm.minnum.f32(float %max, float 4.0)
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store volatile float %med, float addrspace(1)* %outgep
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store volatile float %max, float addrspace(1)* %outgep
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ret void
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}
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; GCN-LABEL: {{^}}v_test_fmed3_r_i_i_f64:
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; GCN: v_max_f64 {{v\[[0-9]+:[0-9]+\]}}, 2.0, {{v\[[0-9]+:[0-9]+\]}}
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; GCN: v_min_f64 {{v\[[0-9]+:[0-9]+\]}}, 4.0, {{v\[[0-9]+:[0-9]+\]}}
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define void @v_test_fmed3_r_i_i_f64(double addrspace(1)* %out, double addrspace(1)* %aptr) #1 {
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%tid = call i32 @llvm.r600.read.tidig.x()
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%gep0 = getelementptr double, double addrspace(1)* %aptr, i32 %tid
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%outgep = getelementptr double, double addrspace(1)* %out, i32 %tid
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%a = load double, double addrspace(1)* %gep0
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%max = call double @llvm.maxnum.f64(double %a, double 2.0)
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||||
%med = call double @llvm.minnum.f64(double %max, double 4.0)
|
||||
|
||||
store double %med, double addrspace(1)* %outgep
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_test_fmed3_r_i_i_no_nans_f32:
|
||||
; GCN: v_med3_f32 v{{[0-9]+}}, v{{[0-9]+}}, 2.0, 4.0
|
||||
define void @v_test_fmed3_r_i_i_no_nans_f32(float addrspace(1)* %out, float addrspace(1)* %aptr) #2 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x()
|
||||
%gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid
|
||||
%outgep = getelementptr float, float addrspace(1)* %out, i32 %tid
|
||||
%a = load float, float addrspace(1)* %gep0
|
||||
|
||||
%max = call float @llvm.maxnum.f32(float %a, float 2.0)
|
||||
%med = call float @llvm.minnum.f32(float %max, float 4.0)
|
||||
|
||||
store float %med, float addrspace(1)* %outgep
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind readnone }
|
||||
attributes #1 = { nounwind "unsafe-fp-math"="false" "no-nans-fp-math"="false" }
|
||||
attributes #2 = { nounwind "unsafe-fp-math"="false" "no-nans-fp-math"="true" }
|
||||
120
test/CodeGen/AMDGPU/smed3.ll
Normal file
120
test/CodeGen/AMDGPU/smed3.ll
Normal file
@ -0,0 +1,120 @@
|
||||
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
|
||||
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
|
||||
|
||||
declare i32 @llvm.r600.read.tidig.x() #0
|
||||
|
||||
; GCN-LABEL: {{^}}v_test_smed3_r_i_i_i32:
|
||||
; GCN: v_med3_i32 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17
|
||||
define void @v_test_smed3_r_i_i_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x()
|
||||
%gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
|
||||
%outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
||||
%a = load i32, i32 addrspace(1)* %gep0
|
||||
|
||||
%icmp0 = icmp sgt i32 %a, 12
|
||||
%i0 = select i1 %icmp0, i32 %a, i32 12
|
||||
|
||||
%icmp1 = icmp slt i32 %i0, 17
|
||||
%i1 = select i1 %icmp1, i32 %i0, i32 17
|
||||
|
||||
store i32 %i1, i32 addrspace(1)* %outgep
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_test_smed3_multi_use_r_i_i_i32:
|
||||
; GCN: v_max_i32
|
||||
; GCN: v_min_i32
|
||||
define void @v_test_smed3_multi_use_r_i_i_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x()
|
||||
%gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
|
||||
%outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
||||
%a = load i32, i32 addrspace(1)* %gep0
|
||||
|
||||
%icmp0 = icmp sgt i32 %a, 12
|
||||
%i0 = select i1 %icmp0, i32 %a, i32 12
|
||||
|
||||
%icmp1 = icmp slt i32 %i0, 17
|
||||
%i1 = select i1 %icmp1, i32 %i0, i32 17
|
||||
|
||||
store volatile i32 %i0, i32 addrspace(1)* %outgep
|
||||
store volatile i32 %i1, i32 addrspace(1)* %outgep
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_test_smed3_r_i_i_constant_order_i32:
|
||||
; GCN: v_max_i32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}}
|
||||
; GCN: v_min_i32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}}
|
||||
define void @v_test_smed3_r_i_i_constant_order_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x()
|
||||
%gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
|
||||
%outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
||||
%a = load i32, i32 addrspace(1)* %gep0
|
||||
|
||||
%icmp0 = icmp sgt i32 %a, 17
|
||||
%i0 = select i1 %icmp0, i32 %a, i32 17
|
||||
|
||||
%icmp1 = icmp slt i32 %i0, 12
|
||||
%i1 = select i1 %icmp1, i32 %i0, i32 12
|
||||
|
||||
store i32 %i1, i32 addrspace(1)* %outgep
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_test_smed3_r_i_i_sign_mismatch_i32:
|
||||
; GCN: v_max_u32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}}
|
||||
; GCN: v_min_i32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}}
|
||||
define void @v_test_smed3_r_i_i_sign_mismatch_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x()
|
||||
%gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
|
||||
%outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
||||
%a = load i32, i32 addrspace(1)* %gep0
|
||||
|
||||
%icmp0 = icmp ugt i32 %a, 12
|
||||
%i0 = select i1 %icmp0, i32 %a, i32 12
|
||||
|
||||
%icmp1 = icmp slt i32 %i0, 17
|
||||
%i1 = select i1 %icmp1, i32 %i0, i32 17
|
||||
|
||||
store i32 %i1, i32 addrspace(1)* %outgep
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_test_smed3_r_i_i_i64:
|
||||
; GCN: v_cmp_lt_i64
|
||||
; GCN: v_cmp_gt_i64
|
||||
define void @v_test_smed3_r_i_i_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) #1 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x()
|
||||
%gep0 = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
|
||||
%outgep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
|
||||
%a = load i64, i64 addrspace(1)* %gep0
|
||||
|
||||
%icmp0 = icmp sgt i64 %a, 12
|
||||
%i0 = select i1 %icmp0, i64 %a, i64 12
|
||||
|
||||
%icmp1 = icmp slt i64 %i0, 17
|
||||
%i1 = select i1 %icmp1, i64 %i0, i64 17
|
||||
|
||||
store i64 %i1, i64 addrspace(1)* %outgep
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_test_smed3_r_i_i_i16:
|
||||
; GCN: v_med3_i32 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17
|
||||
define void @v_test_smed3_r_i_i_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr) #1 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x()
|
||||
%gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
|
||||
%outgep = getelementptr i16, i16 addrspace(1)* %out, i32 %tid
|
||||
%a = load i16, i16 addrspace(1)* %gep0
|
||||
|
||||
%icmp0 = icmp sgt i16 %a, 12
|
||||
%i0 = select i1 %icmp0, i16 %a, i16 12
|
||||
|
||||
%icmp1 = icmp slt i16 %i0, 17
|
||||
%i1 = select i1 %icmp1, i16 %i0, i16 17
|
||||
|
||||
store i16 %i1, i16 addrspace(1)* %outgep
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind readnone }
|
||||
attributes #1 = { nounwind }
|
||||
119
test/CodeGen/AMDGPU/umed3.ll
Normal file
119
test/CodeGen/AMDGPU/umed3.ll
Normal file
@ -0,0 +1,119 @@
|
||||
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
|
||||
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
|
||||
|
||||
declare i32 @llvm.r600.read.tidig.x() #0
|
||||
|
||||
; GCN-LABEL: {{^}}v_test_umed3_r_i_i_i32:
|
||||
; GCN: v_med3_u32 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17
|
||||
define void @v_test_umed3_r_i_i_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x()
|
||||
%gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
|
||||
%outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
||||
%a = load i32, i32 addrspace(1)* %gep0
|
||||
|
||||
%icmp0 = icmp ugt i32 %a, 12
|
||||
%i0 = select i1 %icmp0, i32 %a, i32 12
|
||||
|
||||
%icmp1 = icmp ult i32 %i0, 17
|
||||
%i1 = select i1 %icmp1, i32 %i0, i32 17
|
||||
|
||||
store i32 %i1, i32 addrspace(1)* %outgep
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_test_umed3_multi_use_r_i_i_i32:
|
||||
; GCN: v_max_u32
|
||||
; GCN: v_min_u32
|
||||
define void @v_test_umed3_multi_use_r_i_i_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x()
|
||||
%gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
|
||||
%outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
||||
%a = load i32, i32 addrspace(1)* %gep0
|
||||
|
||||
%icmp0 = icmp ugt i32 %a, 12
|
||||
%i0 = select i1 %icmp0, i32 %a, i32 12
|
||||
|
||||
%icmp1 = icmp ult i32 %i0, 17
|
||||
%i1 = select i1 %icmp1, i32 %i0, i32 17
|
||||
|
||||
store volatile i32 %i0, i32 addrspace(1)* %outgep
|
||||
store volatile i32 %i1, i32 addrspace(1)* %outgep
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_test_umed3_r_i_i_constant_order_i32:
|
||||
; GCN: v_max_u32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}}
|
||||
; GCN: v_min_u32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}}
|
||||
define void @v_test_umed3_r_i_i_constant_order_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x()
|
||||
%gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
|
||||
%outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
||||
%a = load i32, i32 addrspace(1)* %gep0
|
||||
|
||||
%icmp0 = icmp ugt i32 %a, 17
|
||||
%i0 = select i1 %icmp0, i32 %a, i32 17
|
||||
|
||||
%icmp1 = icmp ult i32 %i0, 12
|
||||
%i1 = select i1 %icmp1, i32 %i0, i32 12
|
||||
|
||||
store i32 %i1, i32 addrspace(1)* %outgep
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_test_umed3_r_i_i_sign_mismatch_i32:
|
||||
; GCN: v_max_i32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}}
|
||||
; GCN: v_min_u32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}}
|
||||
define void @v_test_umed3_r_i_i_sign_mismatch_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x()
|
||||
%gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
|
||||
%outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
||||
%a = load i32, i32 addrspace(1)* %gep0
|
||||
|
||||
%icmp0 = icmp sgt i32 %a, 12
|
||||
%i0 = select i1 %icmp0, i32 %a, i32 12
|
||||
|
||||
%icmp1 = icmp ult i32 %i0, 17
|
||||
%i1 = select i1 %icmp1, i32 %i0, i32 17
|
||||
|
||||
store i32 %i1, i32 addrspace(1)* %outgep
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_test_umed3_r_i_i_i64:
|
||||
; GCN: v_cmp_lt_u64
|
||||
; GCN: v_cmp_gt_u64
|
||||
define void @v_test_umed3_r_i_i_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) #1 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x()
|
||||
%gep0 = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
|
||||
%outgep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
|
||||
%a = load i64, i64 addrspace(1)* %gep0
|
||||
|
||||
%icmp0 = icmp ugt i64 %a, 12
|
||||
%i0 = select i1 %icmp0, i64 %a, i64 12
|
||||
|
||||
%icmp1 = icmp ult i64 %i0, 17
|
||||
%i1 = select i1 %icmp1, i64 %i0, i64 17
|
||||
|
||||
store i64 %i1, i64 addrspace(1)* %outgep
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_test_umed3_r_i_i_i16:
|
||||
; GCN: v_med3_u32 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17
|
||||
define void @v_test_umed3_r_i_i_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr) #1 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x()
|
||||
%gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
|
||||
%outgep = getelementptr i16, i16 addrspace(1)* %out, i32 %tid
|
||||
%a = load i16, i16 addrspace(1)* %gep0
|
||||
|
||||
%icmp0 = icmp ugt i16 %a, 12
|
||||
%i0 = select i1 %icmp0, i16 %a, i16 12
|
||||
|
||||
%icmp1 = icmp ult i16 %i0, 17
|
||||
%i1 = select i1 %icmp1, i16 %i0, i16 17
|
||||
|
||||
store i16 %i1, i16 addrspace(1)* %outgep
|
||||
ret void
|
||||
}
|
||||
attributes #0 = { nounwind readnone }
|
||||
attributes #1 = { nounwind }
|
||||
Loading…
Reference in New Issue
Block a user