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Temporarily restore the scavenger implicit_def checking code. MachineOperand isUndef mark is not being put on implicit_def of physical registers (created for parameter passing, etc.).
llvm-svn: 74519
This commit is contained in:
Evan Cheng
parent
c6c942b70f
commit
28b9e77f19
@ -69,6 +69,10 @@ class RegScavenger {
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/// available, unset means the register is currently being used.
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BitVector RegsAvailable;
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/// ImplicitDefed - If bit is set that means the register is defined by an
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/// implicit_def instructions. That means it can be clobbered at will.
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BitVector ImplicitDefed;
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/// CurrDist - Distance from MBB entry to the current instruction MBBI.
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///
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unsigned CurrDist;
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@ -113,18 +117,25 @@ public:
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bool isUsed(unsigned Reg) const { return !RegsAvailable[Reg]; }
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bool isUnused(unsigned Reg) const { return RegsAvailable[Reg]; }
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bool isImplicitlyDefined(unsigned Reg) const { return ImplicitDefed[Reg]; }
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/// getRegsUsed - return all registers currently in use in used.
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void getRegsUsed(BitVector &used, bool includeReserved);
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/// setUsed / setUnused - Mark the state of one or a number of registers.
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///
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void setUsed(unsigned Reg);
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void setUsed(BitVector &Regs) {
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void setUsed(unsigned Reg, bool ImpDef = false);
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void setUsed(BitVector &Regs, bool ImpDef = false) {
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RegsAvailable &= ~Regs;
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if (ImpDef)
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ImplicitDefed |= Regs;
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else
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ImplicitDefed &= ~Regs;
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}
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void setUnused(unsigned Reg, const MachineInstr *MI);
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void setUnused(BitVector &Regs) {
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RegsAvailable |= Regs;
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ImplicitDefed &= ~Regs;
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}
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/// FindUnusedReg - Find a unused register of the specified register class
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@ -57,22 +57,28 @@ static bool RedefinesSuperRegPart(const MachineInstr *MI,
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}
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/// setUsed - Set the register and its sub-registers as being used.
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void RegScavenger::setUsed(unsigned Reg) {
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void RegScavenger::setUsed(unsigned Reg, bool ImpDef) {
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RegsAvailable.reset(Reg);
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ImplicitDefed[Reg] = ImpDef;
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs)
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unsigned SubReg = *SubRegs; ++SubRegs) {
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RegsAvailable.reset(SubReg);
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ImplicitDefed[SubReg] = ImpDef;
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}
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}
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/// setUnused - Set the register and its sub-registers as being unused.
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void RegScavenger::setUnused(unsigned Reg, const MachineInstr *MI) {
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RegsAvailable.set(Reg);
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ImplicitDefed.reset(Reg);
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs)
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if (!RedefinesSuperRegPart(MI, Reg, TRI))
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if (!RedefinesSuperRegPart(MI, Reg, TRI)) {
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RegsAvailable.set(SubReg);
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ImplicitDefed.reset(SubReg);
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}
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}
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void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
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@ -88,6 +94,7 @@ void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
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if (!MBB) {
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NumPhysRegs = TRI->getNumRegs();
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RegsAvailable.resize(NumPhysRegs);
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ImplicitDefed.resize(NumPhysRegs);
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// Create reserved registers bitvector.
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ReservedRegs = TRI->getReservedRegs(MF);
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@ -106,6 +113,7 @@ void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
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ScavengeRestore = NULL;
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CurrDist = 0;
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DistanceMap.clear();
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ImplicitDefed.reset();
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// All registers started out unused.
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RegsAvailable.set();
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@ -187,6 +195,8 @@ void RegScavenger::forward() {
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ScavengeRestore = NULL;
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}
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bool IsImpDef = MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF;
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// Separate register operands into 3 classes: uses, defs, earlyclobbers.
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SmallVector<std::pair<const MachineOperand*,unsigned>, 4> UseMOs;
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SmallVector<std::pair<const MachineOperand*,unsigned>, 4> DefMOs;
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@ -211,7 +221,14 @@ void RegScavenger::forward() {
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assert(isUsed(Reg) && "Using an undefined register!");
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if (MO.isKill() && !isReserved(Reg)) {
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// Kill of implicit_def defined registers are ignored. e.g.
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// entry: 0x2029ab8, LLVM BB @0x1b06080, ID#0:
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// Live Ins: %R0
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// %R0<def> = IMPLICIT_DEF
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// %R0<def> = IMPLICIT_DEF
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// STR %R0<kill>, %R0, %reg0, 0, 14, %reg0, Mem:ST(4,4) [0x1b06510 + 0]
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// %R1<def> = LDR %R0, %reg0, 24, 14, %reg0, Mem:LD(4,4) [0x1b065bc + 0]
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if (MO.isKill() && !isReserved(Reg) && !isImplicitlyDefined(Reg)) {
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KillRegs.set(Reg);
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// Mark sub-registers as used.
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@ -257,9 +274,10 @@ void RegScavenger::forward() {
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// Implicit def is allowed to "re-define" any register. Similarly,
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// implicitly defined registers can be clobbered.
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assert((isReserved(Reg) || isUnused(Reg) ||
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IsImpDef || isImplicitlyDefined(Reg) ||
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isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
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"Re-defining a live register!");
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setUsed(Reg);
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setUsed(Reg, IsImpDef);
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}
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}
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116
test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll
Normal file
116
test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll
Normal file
@ -0,0 +1,116 @@
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; RUN: llvm-as < %s | llc -march=arm -mtriple=armv6-apple-darwin9
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@no_mat = external global i32 ; <i32*> [#uses=1]
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@no_mis = external global i32 ; <i32*> [#uses=2]
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@"\01LC11" = external constant [33 x i8], align 1 ; <[33 x i8]*> [#uses=1]
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@"\01LC15" = external constant [33 x i8], align 1 ; <[33 x i8]*> [#uses=1]
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@"\01LC17" = external constant [47 x i8], align 1 ; <[47 x i8]*> [#uses=1]
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declare arm_apcscc i32 @printf(i8* nocapture, ...) nounwind
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declare arm_apcscc void @diff(i8*, i8*, i32, i32, i32, i32) nounwind
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define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
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entry:
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br i1 undef, label %bb5, label %bb
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bb: ; preds = %bb, %entry
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br label %bb
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bb5: ; preds = %entry
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br i1 undef, label %bb6, label %bb8
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bb6: ; preds = %bb6, %bb5
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br i1 undef, label %bb8, label %bb6
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bb8: ; preds = %bb6, %bb5
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br label %bb15
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bb9: ; preds = %bb15
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br i1 undef, label %bb10, label %bb11
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bb10: ; preds = %bb9
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unreachable
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bb11: ; preds = %bb9
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%0 = load i32* undef, align 4 ; <i32> [#uses=3]
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%1 = add i32 %0, 1 ; <i32> [#uses=2]
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store i32 %1, i32* undef, align 4
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%2 = load i32* undef, align 4 ; <i32> [#uses=2]
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%3 = sub i32 %2, %0 ; <i32> [#uses=1]
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store i32 0, i32* @no_mat, align 4
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store i32 0, i32* @no_mis, align 4
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%4 = getelementptr i8* %B, i32 %0 ; <i8*> [#uses=1]
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tail call arm_apcscc void @diff(i8* undef, i8* %4, i32 undef, i32 %3, i32 undef, i32 undef) nounwind
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%5 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC11", i32 0, i32 0), i32 %tmp13) nounwind ; <i32> [#uses=0]
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%6 = load i32* @no_mis, align 4 ; <i32> [#uses=1]
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%7 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC15", i32 0, i32 0), i32 %6) nounwind ; <i32> [#uses=0]
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%8 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 %2) nounwind ; <i32> [#uses=0]
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br i1 undef, label %bb15, label %bb12
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bb12: ; preds = %bb11
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br label %bb228.i
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bb74.i: ; preds = %bb228.i
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br i1 undef, label %bb138.i, label %bb145.i
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bb138.i: ; preds = %bb74.i
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br label %bb145.i
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bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i
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br i1 undef, label %bb146.i, label %bb151.i
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bb146.i: ; preds = %bb145.i
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br i1 undef, label %bb228.i, label %bb151.i
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bb151.i: ; preds = %bb146.i, %bb145.i
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br i1 undef, label %bb153.i, label %bb228.i
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bb153.i: ; preds = %bb151.i
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br i1 undef, label %bb220.i, label %bb.nph.i98
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bb.nph.i98: ; preds = %bb153.i
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br label %bb158.i
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bb158.i: ; preds = %bb218.i, %bb.nph.i98
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br i1 undef, label %bb168.i, label %bb160.i
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bb160.i: ; preds = %bb158.i
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br i1 undef, label %bb161.i, label %bb168.i
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bb161.i: ; preds = %bb160.i
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br i1 undef, label %bb168.i, label %bb163.i
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bb163.i: ; preds = %bb161.i
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br i1 undef, label %bb167.i, label %bb168.i
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bb167.i: ; preds = %bb163.i
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br label %bb168.i
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bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i
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br i1 undef, label %bb211.i, label %bb218.i
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bb211.i: ; preds = %bb168.i
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br label %bb218.i
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bb218.i: ; preds = %bb211.i, %bb168.i
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br i1 undef, label %bb220.i, label %bb158.i
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bb220.i: ; preds = %bb218.i, %bb153.i
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br i1 undef, label %bb221.i, label %bb228.i
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bb221.i: ; preds = %bb220.i
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br label %bb228.i
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bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12
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br i1 undef, label %bb74.i, label %bb145.i
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bb15: ; preds = %bb11, %bb8
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%indvar11 = phi i32 [ 0, %bb8 ], [ %tmp13, %bb11 ] ; <i32> [#uses=2]
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%tmp13 = add i32 %indvar11, 1 ; <i32> [#uses=2]
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%count.0 = sub i32 undef, %indvar11 ; <i32> [#uses=0]
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br i1 undef, label %return, label %bb9
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return: ; preds = %bb15
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ret void
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}
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