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llvm-svn: 131455
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@ -2040,3 +2040,29 @@ _clamp2: ## @clamp2
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The move of 0 could be scheduled above the test to make it is xor reg,reg.
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//===---------------------------------------------------------------------===//
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GCC PR48986. We currently compile this:
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void bar(void);
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void yyy(int* p) {
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if (__sync_fetch_and_add(p, -1) == 1)
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bar();
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}
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into:
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movl $-1, %eax
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lock
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xaddl %eax, (%rdi)
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cmpl $1, %eax
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je LBB0_2
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Instead we could generate:
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lock
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dec %rdi
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je LBB0_2
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The trick is to match "fetch_and_add(X, -C) == C".
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//===---------------------------------------------------------------------===//
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