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In LLVM FMA3 operands are dst, src1, src2, src3, however dst is not encoded as it is always src1. This was causing the encoding of the operands to be off by one.
Patch by Chris Bieneman. llvm-svn: 188866
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@ -985,8 +985,14 @@ void Emitter<CodeEmitter>::emitVEXOpcodePrefix(uint64_t TSFlags,
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if (X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
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VEX_R = 0x0;
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if (HasVEX_4V)
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VEX_4V = getVEXRegisterEncoding(MI, 1);
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if (HasVEX_4V) {
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if (HasMemOp4)
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VEX_4V = getVEXRegisterEncoding(MI, 1);
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else
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// FMA3 instructions operands are dst, src1, src2, src3
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// dst and src1 are the same and not encoded separately
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VEX_4V = getVEXRegisterEncoding(MI, 2);
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}
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if (X86II::isX86_64ExtendedReg(
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MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
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18
test/ExecutionEngine/fma3-jit.ll
Normal file
18
test/ExecutionEngine/fma3-jit.ll
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@ -0,0 +1,18 @@
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; RUN: %lli %s | FileCheck %s
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; REQUIRES: fma3
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; CHECK: 12.000000
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@msg_double = internal global [4 x i8] c"%f\0A\00"
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declare i32 @printf(i8*, ...)
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define i32 @main() {
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%fma = tail call double @llvm.fma.f64(double 3.0, double 3.0, double 3.0) nounwind readnone
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%ptr1 = getelementptr [4 x i8]* @msg_double, i32 0, i32 0
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call i32 (i8*,...)* @printf(i8* %ptr1, double %fma)
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ret i32 0
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}
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declare double @llvm.fma.f64(double, double, double) nounwind readnone
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