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Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'
pseudonym. llvm-svn: 116512
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ad0548d742
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@ -645,7 +645,7 @@ void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
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// Encode the shift operation.
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switch (Opcode) {
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default: break;
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case ARM::MOVrx:
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case ARM::RRX:
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// rrx
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Binary |= 0x6 << 4;
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break;
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@ -748,7 +748,7 @@ void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
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// Materialize jumptable address.
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emitLEApcrelJTInstruction(MI);
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break;
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case ARM::MOVrx:
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case ARM::RRX:
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case ARM::MOVsrl_flag:
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case ARM::MOVsra_flag:
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emitPseudoMoveInstruction(MI);
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@ -1686,9 +1686,9 @@ def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
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Requires<[IsARM, HasV6T2]>;
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let Uses = [CPSR] in
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def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi,
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"mov", "\t$dst, $src, rrx",
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[(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
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def RRX: AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), Pseudo, IIC_iMOVsi,
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"rrx", "\t$Rd, $Rm",
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[(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP;
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// These aren't really mov instructions, but we have to define them this way
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// due to flag operands.
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@ -1598,7 +1598,7 @@ defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
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defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
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let Uses = [CPSR] in {
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def t2MOVrx : T2sI<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi,
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def t2RRX : T2sI<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi,
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"rrx", "\t$dst, $src",
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[(set rGPR:$dst, (ARMrrx rGPR:$src))]> {
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let Inst{31-27} = 0b11101;
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@ -3,7 +3,7 @@
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define i64 @f0(i64 %A, i64 %B) {
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; CHECK: f0
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; CHECK: movs r3, r3, lsr #1
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; CHECK-NEXT: mov r2, r2, rrx
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; CHECK-NEXT: rrx r2, r2
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; CHECK-NEXT: subs r0, r0, r2
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; CHECK-NEXT: sbc r1, r1, r3
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%tmp = bitcast i64 %A to i64
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