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s/getOpCode/getOpcode
llvm-svn: 11332
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@ -594,7 +594,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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unsigned Reg = MI->getOperand(0).getReg();
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O << TII.getName(MI->getOpCode()) << " ";
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O << TII.getName(MI->getOpcode()) << " ";
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printOp(MI->getOperand(0));
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if (MI->getNumOperands() == 2 &&
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(!MI->getOperand(1).isRegister() ||
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@ -627,7 +627,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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(MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate()))
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&& "Bad format for MRMDestReg!");
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O << TII.getName(MI->getOpCode()) << " ";
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O << TII.getName(MI->getOpcode()) << " ";
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printOp(MI->getOperand(0));
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O << ", ";
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printOp(MI->getOperand(1));
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@ -646,7 +646,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
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MI->getOperand(4).isRegister() && "Bad format for MRMDestMem!");
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O << TII.getName(MI->getOpCode()) << " " << sizePtr(Desc) << " ";
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O << TII.getName(MI->getOpcode()) << " " << sizePtr(Desc) << " ";
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printMemReference(MI, 0);
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O << ", ";
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printOp(MI->getOperand(4));
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@ -676,7 +676,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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(MI->getOperand(2).isImmediate())))
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&& "Bad format for MRMSrcReg!");
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O << TII.getName(MI->getOpCode()) << " ";
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O << TII.getName(MI->getOpcode()) << " ";
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printOp(MI->getOperand(0));
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O << ", ";
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printOp(MI->getOperand(1));
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@ -701,7 +701,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
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O << "**";
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O << TII.getName(MI->getOpCode()) << " ";
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O << TII.getName(MI->getOpcode()) << " ";
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printOp(MI->getOperand(0));
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O << ", " << sizePtr(Desc) << " ";
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printMemReference(MI, MI->getNumOperands()-4);
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@ -732,7 +732,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
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O << "**";
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O << TII.getName(MI->getOpCode()) << " ";
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O << TII.getName(MI->getOpcode()) << " ";
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printOp(MI->getOperand(0));
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if (MI->getOperand(MI->getNumOperands()-1).isImmediate()) {
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O << ", ";
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@ -767,7 +767,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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// is misassembled by gas in intel_syntax mode as its 32-bit
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// equivalent "fstp DWORD PTR [...]". Workaround: Output the raw
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// opcode bytes instead of the instruction.
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if (MI->getOpCode() == X86::FSTPr80) {
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if (MI->getOpcode() == X86::FSTPr80) {
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if ((MI->getOperand(0).getReg() == X86::ESP)
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&& (MI->getOperand(1).getImmedValue() == 1)) {
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if (Op3.isImmediate() &&
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@ -788,7 +788,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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// misassembled by gas in intel_syntax mode as its 32-bit
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// equivalent "fld DWORD PTR [...]". Workaround: Output the raw
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// opcode bytes instead of the instruction.
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if (MI->getOpCode() == X86::FLDr80 &&
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if (MI->getOpcode() == X86::FLDr80 &&
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MI->getOperand(0).getReg() == X86::ESP &&
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MI->getOperand(1).getImmedValue() == 1) {
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if (Op3.isImmediate() && Op3.getImmedValue() >= -128 &&
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@ -808,7 +808,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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// 64 bit modes." libopcodes disassembles it as "fild DWORD PTR
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// [...]", which is wrong. Workaround: Output the raw opcode bytes
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// instead of the instruction.
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if (MI->getOpCode() == X86::FILDr64 &&
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if (MI->getOpcode() == X86::FILDr64 &&
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MI->getOperand(0).getReg() == X86::ESP &&
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MI->getOperand(1).getImmedValue() == 1) {
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if (Op3.isImmediate() && Op3.getImmedValue() >= -128 &&
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@ -829,7 +829,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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// "fistpll DWORD PTR [...]", which is wrong. Workaround: Output
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// "fistpll DWORD PTR " instead, which is what libopcodes is
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// expecting to see.
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if (MI->getOpCode() == X86::FISTPr64) {
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if (MI->getOpcode() == X86::FISTPr64) {
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O << "fistpll DWORD PTR ";
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printMemReference(MI, 0);
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if (MI->getNumOperands() == 5) {
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@ -839,7 +839,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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O << "\t# ";
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}
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O << TII.getName(MI->getOpCode()) << " ";
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O << TII.getName(MI->getOpcode()) << " ";
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O << sizePtr(Desc) << " ";
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printMemReference(MI, 0);
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if (MI->getNumOperands() == 5) {
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