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Properly transfer kill / dead info.

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llvm-svn: 31765
This commit is contained in:
Evan Cheng 2006-11-15 20:58:11 +00:00
parent 1b3bde1c1b
commit 2a92afa25d
6 changed files with 82 additions and 41 deletions
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7
lib/Target/Alpha/AlphaRegisterInfo.cpp
View File

@ -104,6 +104,7 @@ MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
// Make sure this is a reg-reg copy.
unsigned Opc = MI->getOpcode();
MachineInstr *NewMI = NULL;
switch(Opc) {
default:
break;
@ -115,18 +116,20 @@ MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
unsigned InReg = MI->getOperand(1).getReg();
Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
return BuildMI(TII, Opc, 3).addReg(InReg).addFrameIndex(FrameIndex)
NewMI = BuildMI(TII, Opc, 3).addReg(InReg).addFrameIndex(FrameIndex)
.addReg(Alpha::F31);
} else { // load -> move
unsigned OutReg = MI->getOperand(0).getReg();
Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
return BuildMI(TII, Opc, 2, OutReg).addFrameIndex(FrameIndex)
NewMI = BuildMI(TII, Opc, 2, OutReg).addFrameIndex(FrameIndex)
.addReg(Alpha::F31);
}
}
break;
}
if (NewMI)
NewMI->copyKillDeadInfo(MI);
return 0;
}

10
lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -147,8 +147,18 @@ MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
// Swap op1/op2
unsigned Reg1 = MI->getOperand(1).getReg();
unsigned Reg2 = MI->getOperand(2).getReg();
bool Reg1IsKill = MI->getOperand(1).isKill();
bool Reg2IsKill = MI->getOperand(2).isKill();
MI->getOperand(2).setReg(Reg1);
MI->getOperand(1).setReg(Reg2);
if (Reg1IsKill)
MI->getOperand(2).setIsKill();
else
MI->getOperand(2).unsetIsKill();
if (Reg2IsKill)
MI->getOperand(1).setIsKill();
else
MI->getOperand(1).unsetIsKill();
// Swap the mask around.
unsigned MB = MI->getOperand(4).getImmedValue();

30
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -337,47 +337,51 @@ MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
// Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
// it takes more than one instruction to store it.
unsigned Opc = MI->getOpcode();
MachineInstr *NewMI = NULL;
if ((Opc == PPC::OR &&
MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
return addFrameReference(BuildMI(TII, PPC::STW,
3).addReg(InReg), FrameIndex);
NewMI = addFrameReference(BuildMI(TII, PPC::STW,
3).addReg(InReg), FrameIndex);
} else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg();
return addFrameReference(BuildMI(TII, PPC::LWZ, 2, OutReg), FrameIndex);
NewMI = addFrameReference(BuildMI(TII, PPC::LWZ, 2, OutReg), FrameIndex);
}
} else if ((Opc == PPC::OR8 &&
MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
return addFrameReference(BuildMI(TII, PPC::STD,
3).addReg(InReg), FrameIndex);
NewMI = addFrameReference(BuildMI(TII, PPC::STD,
3).addReg(InReg), FrameIndex);
} else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg();
return addFrameReference(BuildMI(TII, PPC::LD, 2, OutReg), FrameIndex);
NewMI = addFrameReference(BuildMI(TII, PPC::LD, 2, OutReg), FrameIndex);
}
} else if (Opc == PPC::FMRD) {
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
return addFrameReference(BuildMI(TII, PPC::STFD,
3).addReg(InReg), FrameIndex);
NewMI = addFrameReference(BuildMI(TII, PPC::STFD,
3).addReg(InReg), FrameIndex);
} else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg();
return addFrameReference(BuildMI(TII, PPC::LFD, 2, OutReg), FrameIndex);
NewMI = addFrameReference(BuildMI(TII, PPC::LFD, 2, OutReg), FrameIndex);
}
} else if (Opc == PPC::FMRS) {
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
return addFrameReference(BuildMI(TII, PPC::STFS,
NewMI = addFrameReference(BuildMI(TII, PPC::STFS,
3).addReg(InReg), FrameIndex);
} else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg();
return addFrameReference(BuildMI(TII, PPC::LFS, 2, OutReg), FrameIndex);
NewMI = addFrameReference(BuildMI(TII, PPC::LFS, 2, OutReg), FrameIndex);
}
}
return 0;
if (NewMI)
NewMI->copyKillDeadInfo(MI);
return NewMI;
}
//===----------------------------------------------------------------------===//

14
lib/Target/Sparc/SparcRegisterInfo.cpp
View File

@ -77,15 +77,16 @@ MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
unsigned OpNum,
int FI) const {
bool isFloat = false;
MachineInstr *NewMI = NULL;
switch (MI->getOpcode()) {
case SP::ORrr:
if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
if (OpNum == 0) // COPY -> STORE
return BuildMI(TII, SP::STri, 3).addFrameIndex(FI).addImm(0)
NewMI = BuildMI(TII, SP::STri, 3).addFrameIndex(FI).addImm(0)
.addReg(MI->getOperand(2).getReg());
else // COPY -> LOAD
return BuildMI(TII, SP::LDri, 2, MI->getOperand(0).getReg())
NewMI = BuildMI(TII, SP::LDri, 2, MI->getOperand(0).getReg())
.addFrameIndex(FI).addImm(0);
}
break;
@ -94,14 +95,17 @@ MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
// FALLTHROUGH
case SP::FMOVD:
if (OpNum == 0) // COPY -> STORE
return BuildMI(TII, isFloat ? SP::STFri : SP::STDFri, 3)
NewMI = BuildMI(TII, isFloat ? SP::STFri : SP::STDFri, 3)
.addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
else // COPY -> LOAD
return BuildMI(TII, isFloat ? SP::LDFri : SP::LDDFri, 2,
NewMI = BuildMI(TII, isFloat ? SP::LDFri : SP::LDDFri, 2,
MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
break;
}
return 0;
if (NewMI)
NewMI->copyKillDeadInfo(MI);
return NewMI;
}
const unsigned* SparcRegisterInfo::getCalleeSaveRegs() const {

41
lib/Target/X86/X86InstrInfo.cpp
View File

@ -130,6 +130,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
unsigned Dest = MI->getOperand(0).getReg();
unsigned Src = MI->getOperand(1).getReg();
MachineInstr *NewMI = NULL;
switch (MI->getOpcode()) {
default: break;
case X86::SHUFPSrri: {
@ -140,7 +141,9 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
unsigned C = MI->getOperand(2).getReg();
unsigned M = MI->getOperand(3).getImmedValue();
if (!Subtarget->hasSSE2() || B != C) return 0;
return BuildMI(*this, X86::PSHUFDri, 2, A).addReg(B).addImm(M);
NewMI = BuildMI(*this, X86::PSHUFDri, 2, A).addReg(B).addImm(M);
NewMI->copyKillDeadInfo(MI);
return NewMI;
}
}
@ -157,46 +160,51 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
case X86::INC32r:
case X86::INC64_32r:
assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
return addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src, 1);
NewMI = addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src, 1);
break;
case X86::INC16r:
case X86::INC64_16r:
if (DisableLEA16) return 0;
assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
return addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src, 1);
NewMI = addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src, 1);
break;
case X86::DEC32r:
case X86::DEC64_32r:
assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
return addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src, -1);
NewMI = addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src, -1);
break;
case X86::DEC16r:
case X86::DEC64_16r:
if (DisableLEA16) return 0;
assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
return addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src, -1);
NewMI = addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src, -1);
break;
case X86::ADD32rr:
assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
return addRegReg(BuildMI(*this, X86::LEA32r, 5, Dest), Src,
NewMI = addRegReg(BuildMI(*this, X86::LEA32r, 5, Dest), Src,
MI->getOperand(2).getReg());
break;
case X86::ADD16rr:
if (DisableLEA16) return 0;
assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
return addRegReg(BuildMI(*this, X86::LEA16r, 5, Dest), Src,
NewMI = addRegReg(BuildMI(*this, X86::LEA16r, 5, Dest), Src,
MI->getOperand(2).getReg());
break;
case X86::ADD32ri:
case X86::ADD32ri8:
assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
if (MI->getOperand(2).isImmediate())
return addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src,
NewMI = addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src,
MI->getOperand(2).getImmedValue());
return 0;
break;
case X86::ADD16ri:
case X86::ADD16ri8:
if (DisableLEA16) return 0;
assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
if (MI->getOperand(2).isImmediate())
return addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src,
NewMI = addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src,
MI->getOperand(2).getImmedValue());
break;
case X86::SHL16ri:
if (DisableLEA16) return 0;
case X86::SHL32ri:
@ -208,12 +216,14 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
AM.Scale = 1 << ShAmt;
AM.IndexReg = Src;
unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r;
return addFullAddress(BuildMI(*this, Opc, 5, Dest), AM);
NewMI = addFullAddress(BuildMI(*this, Opc, 5, Dest), AM);
}
break;
}
return 0;
if (NewMI)
NewMI->copyKillDeadInfo(MI);
return NewMI;
}
/// commuteInstruction - We have a few instructions that must be hacked on to
@ -239,7 +249,10 @@ MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
unsigned A = MI->getOperand(0).getReg();
unsigned B = MI->getOperand(1).getReg();
unsigned C = MI->getOperand(2).getReg();
return BuildMI(*this, Opc, 3, A).addReg(C).addReg(B).addImm(Size-Amt);
bool BisKill = MI->getOperand(1).isKill();
bool CisKill = MI->getOperand(2).isKill();
return BuildMI(*this, Opc, 3, A).addReg(C, false, false, CisKill)
.addReg(B, false, false, BisKill).addImm(Size-Amt);
}
default:
return TargetInstrInfo::commuteInstruction(MI);

21
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -291,6 +291,7 @@ MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI,
bool isTwoAddr = NumOps > 1 &&
TII.getOperandConstraint(MI->getOpcode(), 1,TargetInstrInfo::TIED_TO) != -1;
MachineInstr *NewMI = NULL;
// Folding a memory location into the two-address part of a two-address
// instruction is different than folding it other places. It requires
// replacing the *two* registers with the memory location.
@ -465,13 +466,17 @@ MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI,
isTwoAddrFold = true;
} else if (i == 0) { // If operand 0
if (MI->getOpcode() == X86::MOV16r0)
return MakeM0Inst(TII, X86::MOV16mi, FrameIndex, MI);
NewMI = MakeM0Inst(TII, X86::MOV16mi, FrameIndex, MI);
else if (MI->getOpcode() == X86::MOV32r0)
return MakeM0Inst(TII, X86::MOV32mi, FrameIndex, MI);
NewMI = MakeM0Inst(TII, X86::MOV32mi, FrameIndex, MI);
else if (MI->getOpcode() == X86::MOV64r0)
return MakeM0Inst(TII, X86::MOV64mi32, FrameIndex, MI);
NewMI = MakeM0Inst(TII, X86::MOV64mi32, FrameIndex, MI);
else if (MI->getOpcode() == X86::MOV8r0)
return MakeM0Inst(TII, X86::MOV8mi, FrameIndex, MI);
NewMI = MakeM0Inst(TII, X86::MOV8mi, FrameIndex, MI);
if (NewMI) {
NewMI->copyKillDeadInfo(MI);
return NewMI;
}
static const TableEntry OpcodeTable[] = {
{ X86::CMP16ri, X86::CMP16mi },
@ -828,9 +833,11 @@ MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI,
if (const TableEntry *Entry = TableLookup(OpcodeTablePtr, OpcodeTableSize,
fromOpcode)) {
if (isTwoAddrFold)
return FuseTwoAddrInst(Entry->to, FrameIndex, MI, TII);
return FuseInst(Entry->to, i, FrameIndex, MI, TII);
NewMI = FuseTwoAddrInst(Entry->to, FrameIndex, MI, TII);
else
NewMI = FuseInst(Entry->to, i, FrameIndex, MI, TII);
NewMI->copyKillDeadInfo(MI);
return NewMI;
}
}