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AMDGPU: Don't error on ds.ordered intrinsic in function
These should be assumed to be called from a compute context. Also don't use a 2 entry switch over constants.
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54ede9be55
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2c13fd38f3
@ -6081,6 +6081,28 @@ static unsigned getBufferOffsetForMMO(SDValue VOffset,
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cast<ConstantSDNode>(Offset)->getSExtValue();
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}
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static unsigned getDSShaderTypeValue(const MachineFunction &MF) {
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switch (MF.getFunction().getCallingConv()) {
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case CallingConv::AMDGPU_PS:
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return 1;
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case CallingConv::AMDGPU_VS:
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return 2;
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case CallingConv::AMDGPU_GS:
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return 3;
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case CallingConv::AMDGPU_HS:
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case CallingConv::AMDGPU_LS:
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case CallingConv::AMDGPU_ES:
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report_fatal_error("ds_ordered_count unsupported for this calling conv");
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case CallingConv::AMDGPU_CS:
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case CallingConv::AMDGPU_KERNEL:
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case CallingConv::C:
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case CallingConv::Fast:
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default:
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// Assume other calling conventions are various compute callable functions
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return 0;
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}
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}
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SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
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SelectionDAG &DAG) const {
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unsigned IntrID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
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@ -6096,8 +6118,6 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
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unsigned IndexOperand = M->getConstantOperandVal(7);
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unsigned WaveRelease = M->getConstantOperandVal(8);
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unsigned WaveDone = M->getConstantOperandVal(9);
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unsigned ShaderType;
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unsigned Instruction;
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unsigned OrderedCountIndex = IndexOperand & 0x3f;
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IndexOperand &= ~0x3f;
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@ -6116,36 +6136,11 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
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if (IndexOperand)
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report_fatal_error("ds_ordered_count: bad index operand");
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switch (IntrID) {
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case Intrinsic::amdgcn_ds_ordered_add:
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Instruction = 0;
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break;
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case Intrinsic::amdgcn_ds_ordered_swap:
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Instruction = 1;
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break;
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}
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if (WaveDone && !WaveRelease)
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report_fatal_error("ds_ordered_count: wave_done requires wave_release");
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switch (DAG.getMachineFunction().getFunction().getCallingConv()) {
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case CallingConv::AMDGPU_CS:
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case CallingConv::AMDGPU_KERNEL:
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ShaderType = 0;
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break;
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case CallingConv::AMDGPU_PS:
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ShaderType = 1;
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break;
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case CallingConv::AMDGPU_VS:
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ShaderType = 2;
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break;
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case CallingConv::AMDGPU_GS:
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ShaderType = 3;
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break;
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default:
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report_fatal_error("ds_ordered_count unsupported for this calling conv");
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}
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unsigned Instruction = IntrID == Intrinsic::amdgcn_ds_ordered_add ? 0 : 1;
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unsigned ShaderType = getDSShaderTypeValue(DAG.getMachineFunction());
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unsigned Offset0 = OrderedCountIndex << 2;
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unsigned Offset1 = WaveRelease | (WaveDone << 1) | (ShaderType << 2) |
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(Instruction << 4);
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@ -57,6 +57,42 @@ define amdgpu_cs float @ds_ordered_add_cs(i32 addrspace(2)* inreg %gds) {
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ret float %r
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}
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; FUNC-LABEL: {{^}}ds_ordered_add_default_cc:
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; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
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; GCN: s_mov_b32 m0, 0{{$}}
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; VIGFX9-NEXT: s_nop 0
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; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds
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; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)
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define float @ds_ordered_add_default_cc() {
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%val = call i32 @llvm.amdgcn.ds.ordered.add(i32 addrspace(2)* null, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true)
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%r = bitcast i32 %val to float
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ret float %r
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}
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; FUNC-LABEL: {{^}}ds_ordered_add_fastcc:
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; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
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; GCN: s_mov_b32 m0, 0{{$}}
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; VIGFX9-NEXT: s_nop 0
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; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds
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; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)
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define fastcc float @ds_ordered_add_fastcc() {
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%val = call i32 @llvm.amdgcn.ds.ordered.add(i32 addrspace(2)* null, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true)
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%r = bitcast i32 %val to float
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ret float %r
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}
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; FUNC-LABEL: {{^}}ds_ordered_add_func:
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; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
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; GCN: s_mov_b32 m0, 0{{$}}
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; VIGFX9-NEXT: s_nop 0
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; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds
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; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)
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define float @ds_ordered_add_func() {
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%val = call i32@llvm.amdgcn.ds.ordered.add(i32 addrspace(2)* null, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true)
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%r = bitcast i32 %val to float
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ret float %r
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}
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; FUNC-LABEL: {{^}}ds_ordered_add_ps:
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; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
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; GCN: s_mov_b32 m0, s0
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