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https://github.com/RPCS3/llvm-mirror.git
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Use CHECK-LABEL in MSan IR tests.
This actually found one case when a test was matching instructions from the output of a different test. llvm-svn: 245974
This commit is contained in:
Evgeniy Stepanov
parent
0d55393ca3
commit
2cabb4d677
@ -13,7 +13,7 @@ entry:
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ret i32 %0
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}
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; CHECK: @AtomicRmwXchg
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; CHECK-LABEL: @AtomicRmwXchg
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; CHECK: store i32 0,
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; CHECK: atomicrmw xchg {{.*}} seq_cst
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; CHECK: store i32 0, {{.*}} @__msan_retval_tls
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@ -28,7 +28,7 @@ entry:
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ret i32 %0
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}
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; CHECK: @AtomicRmwMax
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; CHECK-LABEL: @AtomicRmwMax
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; CHECK: store i32 0,
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; CHECK: atomicrmw max {{.*}} seq_cst
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; CHECK: store i32 0, {{.*}} @__msan_retval_tls
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@ -44,7 +44,7 @@ entry:
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ret i32 %0
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}
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; CHECK: @Cmpxchg
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; CHECK-LABEL: @Cmpxchg
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; CHECK: store { i32, i1 } zeroinitializer,
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; CHECK: icmp
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; CHECK: br
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@ -63,7 +63,7 @@ entry:
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ret i32 %0
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}
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; CHECK: @CmpxchgMonotonic
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; CHECK-LABEL: @CmpxchgMonotonic
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; CHECK: store { i32, i1 } zeroinitializer,
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; CHECK: icmp
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; CHECK: br
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@ -81,7 +81,7 @@ entry:
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ret i32 %0
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}
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; CHECK: @AtomicLoad
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; CHECK-LABEL: @AtomicLoad
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; CHECK: load atomic i32, i32* {{.*}} seq_cst, align 16
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; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32, i32* {{.*}}, align 16
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; CHECK: store i32 {{.*}}[[SHADOW]], {{.*}} @__msan_retval_tls
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@ -96,7 +96,7 @@ entry:
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ret i32 %0
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}
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; CHECK: @AtomicLoadAcquire
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; CHECK-LABEL: @AtomicLoadAcquire
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; CHECK: load atomic i32, i32* {{.*}} acquire, align 16
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; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32, i32* {{.*}}, align 16
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; CHECK: store i32 {{.*}}[[SHADOW]], {{.*}} @__msan_retval_tls
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@ -111,7 +111,7 @@ entry:
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ret i32 %0
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}
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; CHECK: @AtomicLoadMonotonic
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; CHECK-LABEL: @AtomicLoadMonotonic
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; CHECK: load atomic i32, i32* {{.*}} acquire, align 16
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; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32, i32* {{.*}}, align 16
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; CHECK: store i32 {{.*}}[[SHADOW]], {{.*}} @__msan_retval_tls
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@ -126,7 +126,7 @@ entry:
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ret i32 %0
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}
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; CHECK: @AtomicLoadUnordered
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; CHECK-LABEL: @AtomicLoadUnordered
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; CHECK: load atomic i32, i32* {{.*}} acquire, align 16
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; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32, i32* {{.*}}, align 16
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; CHECK: store i32 {{.*}}[[SHADOW]], {{.*}} @__msan_retval_tls
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@ -141,7 +141,7 @@ entry:
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ret void
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}
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; CHECK: @AtomicStore
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; CHECK-LABEL: @AtomicStore
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; CHECK-NOT: @__msan_param_tls
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; CHECK: store i32 0, i32* {{.*}}, align 16
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; CHECK: store atomic i32 %x, i32* %p seq_cst, align 16
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@ -156,7 +156,7 @@ entry:
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ret void
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}
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; CHECK: @AtomicStoreRelease
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; CHECK-LABEL: @AtomicStoreRelease
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; CHECK-NOT: @__msan_param_tls
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; CHECK: store i32 0, i32* {{.*}}, align 16
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; CHECK: store atomic i32 %x, i32* %p release, align 16
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@ -171,7 +171,7 @@ entry:
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ret void
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}
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; CHECK: @AtomicStoreMonotonic
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; CHECK-LABEL: @AtomicStoreMonotonic
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; CHECK-NOT: @__msan_param_tls
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; CHECK: store i32 0, i32* {{.*}}, align 16
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; CHECK: store atomic i32 %x, i32* %p release, align 16
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@ -186,7 +186,7 @@ entry:
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ret void
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}
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; CHECK: @AtomicStoreUnordered
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; CHECK-LABEL: @AtomicStoreUnordered
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; CHECK-NOT: @__msan_param_tls
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; CHECK: store i32 0, i32* {{.*}}, align 16
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; CHECK: store atomic i32 %x, i32* %p release, align 16
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@ -12,7 +12,7 @@ entry:
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ret <2 x i64> %x
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}
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; CHECK: @ByValArgumentShadowLargeAlignment
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; CHECK-LABEL: @ByValArgumentShadowLargeAlignment
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; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* {{.*}}, i8* {{.*}}, i64 16, i32 8, i1 false)
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; CHECK: ret <2 x i64>
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@ -23,6 +23,6 @@ entry:
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ret i16 %x
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}
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; CHECK: @ByValArgumentShadowSmallAlignment
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; CHECK-LABEL: @ByValArgumentShadowSmallAlignment
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; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* {{.*}}, i8* {{.*}}, i64 2, i32 2, i1 false)
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; CHECK: ret i16
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@ -28,7 +28,7 @@ entry:
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ret void
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}
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; CHECK: @Store
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; CHECK-LABEL: @Store
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; CHECK: load {{.*}} @__msan_param_tls
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; CHECK-ORIGINS: load {{.*}} @__msan_param_origin_tls
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; CHECK: store
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@ -52,7 +52,7 @@ entry:
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ret void
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}
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; CHECK: @AlignedStore
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; CHECK-LABEL: @AlignedStore
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; CHECK: load {{.*}} @__msan_param_tls
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; CHECK-ORIGINS: load {{.*}} @__msan_param_origin_tls
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; CHECK: store {{.*}} align 32
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@ -83,7 +83,7 @@ if.end: ; preds = %entry, %if.then
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declare void @foo(...)
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; CHECK: @LoadAndCmp
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; CHECK-LABEL: @LoadAndCmp
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; CHECK: = load
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; CHECK: = load
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; CHECK: call void @__msan_warning_noreturn()
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@ -97,7 +97,7 @@ entry:
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ret i32 123
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}
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; CHECK: @ReturnInt
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; CHECK-LABEL: @ReturnInt
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; CHECK: store i32 0,{{.*}}__msan_retval_tls
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; CHECK: ret i32
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@ -109,7 +109,7 @@ entry:
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ret void
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}
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; CHECK: @CopyRetVal
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; CHECK-LABEL: @CopyRetVal
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; CHECK: load{{.*}}__msan_retval_tls
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; CHECK: store
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; CHECK: store
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@ -136,7 +136,7 @@ entry:
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ret void
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}
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; CHECK: @FuncWithPhi
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; CHECK-LABEL: @FuncWithPhi
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; CHECK: = phi
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; CHECK-NEXT: = phi
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; CHECK: store
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@ -152,7 +152,7 @@ entry:
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ret void
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}
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; CHECK: @ShlConst
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; CHECK-LABEL: @ShlConst
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; CHECK: = load
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; CHECK: = load
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; CHECK: shl
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@ -170,7 +170,7 @@ entry:
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ret void
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}
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; CHECK: @ShlNonConst
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; CHECK-LABEL: @ShlNonConst
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; CHECK: = load
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; CHECK: = load
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; CHECK: = sext i1
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@ -187,7 +187,7 @@ entry:
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ret void
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}
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; CHECK: @SExt
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; CHECK-LABEL: @SExt
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; CHECK: = load
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; CHECK: = load
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; CHECK: = sext
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@ -206,7 +206,7 @@ entry:
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declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
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; CHECK: @MemSet
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; CHECK-LABEL: @MemSet
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; CHECK: call i8* @__msan_memset
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; CHECK: ret void
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@ -220,7 +220,7 @@ entry:
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
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; CHECK: @MemCpy
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; CHECK-LABEL: @MemCpy
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; CHECK: call i8* @__msan_memcpy
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; CHECK: ret void
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@ -234,7 +234,7 @@ entry:
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declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
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; CHECK: @MemMove
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; CHECK-LABEL: @MemMove
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; CHECK: call i8* @__msan_memmove
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; CHECK: ret void
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@ -247,7 +247,7 @@ entry:
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ret i32 %cond
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}
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; CHECK: @Select
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; CHECK-LABEL: @Select
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; CHECK: select i1
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; CHECK-DAG: or i32
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; CHECK-DAG: xor i32
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@ -271,7 +271,7 @@ entry:
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ret <8 x i16> %cond
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}
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; CHECK: @SelectVector
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; CHECK-LABEL: @SelectVector
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; CHECK: select <8 x i1>
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; CHECK-DAG: or <8 x i16>
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; CHECK-DAG: xor <8 x i16>
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@ -295,7 +295,7 @@ entry:
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ret <8 x i16> %cond
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}
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; CHECK: @SelectVector2
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; CHECK-LABEL: @SelectVector2
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; CHECK: select i1
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; CHECK-DAG: or <8 x i16>
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; CHECK-DAG: xor <8 x i16>
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@ -313,7 +313,7 @@ entry:
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ret { i64, i64 } %c
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}
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; CHECK: @SelectStruct
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; CHECK-LABEL: @SelectStruct
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; CHECK: select i1 {{.*}}, { i64, i64 }
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; CHECK-NEXT: select i1 {{.*}}, { i64, i64 } { i64 -1, i64 -1 }, { i64, i64 }
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; CHECK-ORIGINS: select i1
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@ -328,7 +328,7 @@ entry:
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ret { i64*, double } %c
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}
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; CHECK: @SelectStruct2
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; CHECK-LABEL: @SelectStruct2
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; CHECK: select i1 {{.*}}, { i64, i64 }
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; CHECK-NEXT: select i1 {{.*}}, { i64, i64 } { i64 -1, i64 -1 }, { i64, i64 }
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; CHECK-ORIGINS: select i1
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@ -343,7 +343,7 @@ entry:
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ret i8* %0
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}
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; CHECK: @IntToPtr
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; CHECK-LABEL: @IntToPtr
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; CHECK: load i64, i64*{{.*}}__msan_param_tls
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; CHECK-ORIGINS-NEXT: load i32, i32*{{.*}}__msan_param_origin_tls
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; CHECK-NEXT: inttoptr
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@ -357,7 +357,7 @@ entry:
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ret i8* %0
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}
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; CHECK: @IntToPtr_ZExt
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; CHECK-LABEL: @IntToPtr_ZExt
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; CHECK: load i16, i16*{{.*}}__msan_param_tls
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; CHECK: zext
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; CHECK-NEXT: inttoptr
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@ -374,7 +374,7 @@ entry:
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ret i32 %div
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}
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; CHECK: @Div
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; CHECK-LABEL: @Div
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; CHECK: icmp
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; CHECK: call void @__msan_warning
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; CHECK-NOT: icmp
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@ -390,7 +390,7 @@ define zeroext i1 @ICmpSLT(i32 %x) nounwind uwtable readnone sanitize_memory {
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ret i1 %1
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}
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; CHECK: @ICmpSLT
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; CHECK-LABEL: @ICmpSLT
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; CHECK: icmp slt
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; CHECK-NOT: call void @__msan_warning
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; CHECK: icmp slt
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@ -402,7 +402,7 @@ define zeroext i1 @ICmpSGE(i32 %x) nounwind uwtable readnone sanitize_memory {
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ret i1 %1
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}
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; CHECK: @ICmpSGE
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; CHECK-LABEL: @ICmpSGE
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; CHECK: icmp slt
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; CHECK-NOT: call void @__msan_warning
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; CHECK: icmp sge
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@ -414,7 +414,7 @@ define zeroext i1 @ICmpSGT(i32 %x) nounwind uwtable readnone sanitize_memory {
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ret i1 %1
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}
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; CHECK: @ICmpSGT
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; CHECK-LABEL: @ICmpSGT
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; CHECK: icmp slt
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; CHECK-NOT: call void @__msan_warning
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; CHECK: icmp sgt
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@ -426,7 +426,7 @@ define zeroext i1 @ICmpSLE(i32 %x) nounwind uwtable readnone sanitize_memory {
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ret i1 %1
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}
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; CHECK: @ICmpSLE
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; CHECK-LABEL: @ICmpSLE
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; CHECK: icmp slt
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; CHECK-NOT: call void @__msan_warning
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; CHECK: icmp sle
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@ -442,7 +442,7 @@ define <2 x i1> @ICmpSLT_vector(<2 x i32*> %x) nounwind uwtable readnone sanitiz
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ret <2 x i1> %1
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}
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; CHECK: @ICmpSLT_vector
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; CHECK-LABEL: @ICmpSLT_vector
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; CHECK: icmp slt <2 x i64>
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; CHECK-NOT: call void @__msan_warning
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; CHECK: icmp slt <2 x i32*>
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@ -459,7 +459,7 @@ entry:
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ret i1 %cmp
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}
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; CHECK: @ICmpUGTConst
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; CHECK-LABEL: @ICmpUGTConst
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; CHECK: icmp ugt i32
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; CHECK-NOT: call void @__msan_warning
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; CHECK: icmp ugt i32
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@ -478,7 +478,7 @@ define i32 @ShadowLoadAlignmentLarge() nounwind uwtable sanitize_memory {
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ret i32 %1
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}
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; CHECK: @ShadowLoadAlignmentLarge
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; CHECK-LABEL: @ShadowLoadAlignmentLarge
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; CHECK: load volatile i32, i32* {{.*}} align 64
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; CHECK: load i32, i32* {{.*}} align 64
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; CHECK: ret i32
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@ -489,7 +489,7 @@ define i32 @ShadowLoadAlignmentSmall() nounwind uwtable sanitize_memory {
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ret i32 %1
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}
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; CHECK: @ShadowLoadAlignmentSmall
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; CHECK-LABEL: @ShadowLoadAlignmentSmall
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; CHECK: load volatile i32, i32* {{.*}} align 2
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; CHECK: load i32, i32* {{.*}} align 2
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; CHECK-ORIGINS: load i32, i32* {{.*}} align 4
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@ -505,7 +505,7 @@ define i32 @ExtractElement(<4 x i32> %vec, i32 %idx) sanitize_memory {
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ret i32 %x
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}
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; CHECK: @ExtractElement
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; CHECK-LABEL: @ExtractElement
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; CHECK: extractelement
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; CHECK: call void @__msan_warning
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; CHECK: extractelement
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@ -516,7 +516,7 @@ define <4 x i32> @InsertElement(<4 x i32> %vec, i32 %idx, i32 %x) sanitize_memor
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ret <4 x i32> %vec1
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}
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; CHECK: @InsertElement
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; CHECK-LABEL: @InsertElement
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; CHECK: insertelement
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; CHECK: call void @__msan_warning
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; CHECK: insertelement
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@ -528,7 +528,7 @@ define <4 x i32> @ShuffleVector(<4 x i32> %vec, <4 x i32> %vec1) sanitize_memory
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ret <4 x i32> %vec2
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}
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; CHECK: @ShuffleVector
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; CHECK-LABEL: @ShuffleVector
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; CHECK: shufflevector
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; CHECK-NOT: call void @__msan_warning
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; CHECK: shufflevector
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@ -543,7 +543,7 @@ define i32 @BSwap(i32 %x) nounwind uwtable readnone sanitize_memory {
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declare i32 @llvm.bswap.i32(i32) nounwind readnone
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; CHECK: @BSwap
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; CHECK-LABEL: @BSwap
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; CHECK-NOT: call void @__msan_warning
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; CHECK: @llvm.bswap.i32
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; CHECK-NOT: call void @__msan_warning
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@ -561,7 +561,7 @@ define void @StoreIntrinsic(i8* %p, <4 x float> %x) nounwind uwtable sanitize_me
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declare void @llvm.x86.sse.storeu.ps(i8*, <4 x float>) nounwind
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; CHECK: @StoreIntrinsic
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; CHECK-LABEL: @StoreIntrinsic
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; CHECK-NOT: br
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; CHECK-NOT: = or
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; CHECK: store <4 x i32> {{.*}} align 1
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@ -578,7 +578,7 @@ define <16 x i8> @LoadIntrinsic(i8* %p) nounwind uwtable sanitize_memory {
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declare <16 x i8> @llvm.x86.sse3.ldu.dq(i8* %p) nounwind
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; CHECK: @LoadIntrinsic
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; CHECK-LABEL: @LoadIntrinsic
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; CHECK: load <16 x i8>, <16 x i8>* {{.*}} align 1
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; CHECK-ORIGINS: [[ORIGIN:%[01-9a-z]+]] = load i32, i32* {{.*}}
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; CHECK-NOT: br
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@ -600,7 +600,7 @@ define <8 x i16> @Paddsw128(<8 x i16> %a, <8 x i16> %b) nounwind uwtable sanitiz
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declare <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %a, <8 x i16> %b) nounwind
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; CHECK: @Paddsw128
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; CHECK-LABEL: @Paddsw128
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; CHECK-NEXT: load <8 x i16>, <8 x i16>* {{.*}} @__msan_param_tls
|
||||
; CHECK-ORIGINS: load i32, i32* {{.*}} @__msan_param_origin_tls
|
||||
; CHECK-NEXT: load <8 x i16>, <8 x i16>* {{.*}} @__msan_param_tls
|
||||
@ -623,7 +623,7 @@ define <8 x i8*> @VectorOfPointers(<8 x i8*>* %p) nounwind uwtable sanitize_memo
|
||||
ret <8 x i8*> %x
|
||||
}
|
||||
|
||||
; CHECK: @VectorOfPointers
|
||||
; CHECK-LABEL: @VectorOfPointers
|
||||
; CHECK: load <8 x i8*>, <8 x i8*>*
|
||||
; CHECK: load <8 x i64>, <8 x i64>*
|
||||
; CHECK: store <8 x i64> {{.*}} @__msan_retval_tls
|
||||
@ -638,7 +638,7 @@ define void @VACopy(i8* %p1, i8* %p2) nounwind uwtable sanitize_memory {
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: @VACopy
|
||||
; CHECK-LABEL: @VACopy
|
||||
; CHECK: call void @llvm.memset.p0i8.i64({{.*}}, i8 0, i64 24, i32 8, i1 false)
|
||||
; CHECK: ret void
|
||||
|
||||
@ -661,7 +661,7 @@ entry:
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: @VAStart
|
||||
; CHECK-LABEL: @VAStart
|
||||
; CHECK: call void @llvm.va_start
|
||||
; CHECK-NOT: @__msan_va_arg_tls
|
||||
; CHECK-NOT: @__msan_va_arg_overflow_size_tls
|
||||
@ -677,7 +677,7 @@ entry:
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: @VolatileStore
|
||||
; CHECK-LABEL: @VolatileStore
|
||||
; CHECK-NOT: @__msan_warning
|
||||
; CHECK: ret void
|
||||
|
||||
@ -700,7 +700,7 @@ if.end: ; preds = %entry, %if.then
|
||||
|
||||
declare void @bar()
|
||||
|
||||
; CHECK: @NoSanitizeMemory
|
||||
; CHECK-LABEL: @NoSanitizeMemory
|
||||
; CHECK-NOT: @__msan_warning
|
||||
; CHECK: store i32 0, {{.*}} @__msan_retval_tls
|
||||
; CHECK-NOT: @__msan_warning
|
||||
@ -719,7 +719,7 @@ entry:
|
||||
|
||||
declare i32 @NoSanitizeMemoryAllocaHelper(i32* %p)
|
||||
|
||||
; CHECK: @NoSanitizeMemoryAlloca
|
||||
; CHECK-LABEL: @NoSanitizeMemoryAlloca
|
||||
; CHECK: call void @llvm.memset.p0i8.i64(i8* {{.*}}, i8 0, i64 4, i32 4, i1 false)
|
||||
; CHECK: call i32 @NoSanitizeMemoryAllocaHelper(i32*
|
||||
; CHECK: ret i32
|
||||
@ -736,7 +736,7 @@ entry:
|
||||
|
||||
declare i32 @NoSanitizeMemoryUndefHelper(i32 %x)
|
||||
|
||||
; CHECK: @NoSanitizeMemoryAlloca
|
||||
; CHECK-LABEL: @NoSanitizeMemoryUndef
|
||||
; CHECK: store i32 0, i32* {{.*}} @__msan_param_tls
|
||||
; CHECK: call i32 @NoSanitizeMemoryUndefHelper(i32 undef)
|
||||
; CHECK: ret i32
|
||||
@ -790,7 +790,7 @@ entry:
|
||||
ret <2 x i64> %b
|
||||
}
|
||||
|
||||
; CHECK: @ArgumentShadowAlignment
|
||||
; CHECK-LABEL: @ArgumentShadowAlignment
|
||||
; CHECK: load <2 x i64>, <2 x i64>* {{.*}} @__msan_param_tls {{.*}}, align 8
|
||||
; CHECK: store <2 x i64> {{.*}} @__msan_retval_tls {{.*}}, align 8
|
||||
; CHECK: ret <2 x i64>
|
||||
@ -847,7 +847,7 @@ entry:
|
||||
; "undef" and the first 2 structs go to general purpose registers;
|
||||
; the third struct goes to the overflow area byval
|
||||
|
||||
; CHECK: @VAArgStruct
|
||||
; CHECK-LABEL: @VAArgStruct
|
||||
; undef
|
||||
; CHECK: store i32 -1, i32* {{.*}}@__msan_va_arg_tls {{.*}}, align 8
|
||||
; first struct through general purpose registers
|
||||
|
||||
@ -10,7 +10,7 @@ entry:
|
||||
|
||||
declare i32 @f() sanitize_memory
|
||||
|
||||
; CHECK: @main
|
||||
; CHECK-LABEL: @main
|
||||
; CHECK: call i32 @f()
|
||||
; CHECK: store i32 0, {{.*}} @__msan_retval_tls
|
||||
; CHECK: br i1
|
||||
|
||||
@ -52,7 +52,7 @@ attributes #1 = { nounwind readnone }
|
||||
!22 = !DILocation(line: 3, scope: !4)
|
||||
|
||||
|
||||
; CHECK: @Store
|
||||
; CHECK-LABEL: @Store
|
||||
; CHECK: load {{.*}} @__msan_param_tls
|
||||
; CHECK: [[ORIGIN:%[01-9a-z]+]] = load {{.*}} @__msan_param_origin_tls
|
||||
; CHECK: store {{.*}}!dbg ![[DBG:[01-9]+]]
|
||||
|
||||
@ -18,7 +18,7 @@ exit:
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
; CHECK: @Func
|
||||
; CHECK-LABEL: @Func
|
||||
; CHECK: store i32 0, {{.*}} @__msan_retval_tls
|
||||
; CHECK: ret i32 42
|
||||
|
||||
@ -34,6 +34,6 @@ xxx:
|
||||
br label %zzz
|
||||
}
|
||||
|
||||
; CHECK: @UnreachableLoop
|
||||
; CHECK-LABEL: @UnreachableLoop
|
||||
; CHECK: store i32 0, {{.*}} @__msan_retval_tls
|
||||
; CHECK: ret i32 0
|
||||
|
||||
@ -15,7 +15,7 @@ entry:
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
; CHECK: @test_cvtsd2si
|
||||
; CHECK-LABEL: @test_cvtsd2si
|
||||
; CHECK: [[S:%[_01-9a-z]+]] = extractelement <2 x i64> {{.*}}, i32 0
|
||||
; CHECK: icmp ne {{.*}}[[S]], 0
|
||||
; CHECK: br
|
||||
@ -33,7 +33,7 @@ entry:
|
||||
ret <2 x double> %0
|
||||
}
|
||||
|
||||
; CHECK: @test_cvtsi2sd
|
||||
; CHECK-LABEL: @test_cvtsi2sd
|
||||
; CHECK: [[Sa:%[_01-9a-z]+]] = load i32, i32* {{.*}} @__msan_param_tls
|
||||
; CHECK: [[Sout0:%[_01-9a-z]+]] = insertelement <2 x i64> <i64 -1, i64 -1>, i64 {{.*}}, i32 1
|
||||
; Clear low half of result shadow
|
||||
@ -54,7 +54,7 @@ entry:
|
||||
ret x86_mmx %0
|
||||
}
|
||||
|
||||
; CHECK: @test_cvtps2pi
|
||||
; CHECK-LABEL: @test_cvtps2pi
|
||||
; CHECK: extractelement <4 x i32> {{.*}}, i32 0
|
||||
; CHECK: extractelement <4 x i32> {{.*}}, i32 1
|
||||
; CHECK: [[S:%[_01-9a-z]+]] = or i32
|
||||
|
||||
@ -25,7 +25,7 @@ entry:
|
||||
ret i64 %6
|
||||
}
|
||||
|
||||
; CHECK: @test_mmx
|
||||
; CHECK-LABEL: @test_mmx
|
||||
; CHECK: = icmp ne i64 {{.*}}, 0
|
||||
; CHECK: [[C:%.*]] = sext i1 {{.*}} to i64
|
||||
; CHECK: [[A:%.*]] = call x86_mmx @llvm.x86.mmx.psll.d(
|
||||
@ -41,7 +41,7 @@ entry:
|
||||
ret <8 x i16> %0
|
||||
}
|
||||
|
||||
; CHECK: @test_sse2_scalar
|
||||
; CHECK-LABEL: @test_sse2_scalar
|
||||
; CHECK: = icmp ne i32 {{.*}}, 0
|
||||
; CHECK: = sext i1 {{.*}} to i128
|
||||
; CHECK: = bitcast i128 {{.*}} to <8 x i16>
|
||||
@ -57,7 +57,7 @@ entry:
|
||||
ret <8 x i16> %0
|
||||
}
|
||||
|
||||
; CHECK: @test_sse2
|
||||
; CHECK-LABEL: @test_sse2
|
||||
; CHECK: = bitcast <8 x i16> {{.*}} to i128
|
||||
; CHECK: = trunc i128 {{.*}} to i64
|
||||
; CHECK: = icmp ne i64 {{.*}}, 0
|
||||
@ -77,7 +77,7 @@ entry:
|
||||
ret <4 x i32> %0
|
||||
}
|
||||
|
||||
; CHECK: @test_avx2
|
||||
; CHECK-LABEL: @test_avx2
|
||||
; CHECK: = icmp ne <4 x i32> {{.*}}, zeroinitializer
|
||||
; CHECK: = sext <4 x i1> {{.*}} to <4 x i32>
|
||||
; CHECK: = call <4 x i32> @llvm.x86.avx2.psllv.d(
|
||||
@ -91,7 +91,7 @@ entry:
|
||||
ret <8 x i32> %0
|
||||
}
|
||||
|
||||
; CHECK: @test_avx2_256
|
||||
; CHECK-LABEL: @test_avx2_256
|
||||
; CHECK: = icmp ne <8 x i32> {{.*}}, zeroinitializer
|
||||
; CHECK: = sext <8 x i1> {{.*}} to <8 x i32>
|
||||
; CHECK: = call <8 x i32> @llvm.x86.avx2.psllv.d.256(
|
||||
|
||||
Loading…
Reference in New Issue
Block a user