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Add sqrt, rsqrt and rcp AVX instructions
llvm-svn: 107166
This commit is contained in:
Bruno Cardoso Lopes
parent
151bec3c2d
commit
2dca1dd168
@ -1873,7 +1873,7 @@ let isCommutable = 0 in {
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/// sse1_fp_unop_s - SSE1 unops in scalar form.
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multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
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SDNode OpNode, Intrinsic F32Int> {
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SDNode OpNode, Intrinsic F32Int> {
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def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
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!strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
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[(set FR32:$dst, (OpNode FR32:$src))]>;
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@ -1906,6 +1906,26 @@ multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr,
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[(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
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}
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/// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
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multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
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SDNode OpNode, Intrinsic F32Int> {
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def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
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!strconcat(!strconcat("v", OpcodeStr),
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"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
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def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
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!strconcat(!strconcat("v", OpcodeStr),
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"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, XS, Requires<[HasAVX, HasSSE1, OptForSize]>;
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def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(!strconcat("v", OpcodeStr),
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"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
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def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, ssmem:$src2),
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!strconcat(!strconcat("v", OpcodeStr),
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"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
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}
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/// sse2_fp_unop_s - SSE2 unops in scalar form.
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multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
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SDNode OpNode, Intrinsic F64Int> {
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@ -1940,6 +1960,52 @@ multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
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[(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
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}
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/// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
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multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
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SDNode OpNode, Intrinsic F64Int> {
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def SDr : VSDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
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!strconcat(OpcodeStr,
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"sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
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def SDm : VSDI<opc, MRMSrcMem, (outs FR64:$dst),
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(ins FR64:$src1, f64mem:$src2),
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!strconcat(OpcodeStr,
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"sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
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def SDr_Int : VSDI<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>;
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def SDm_Int : VSDI<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, sdmem:$src2),
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!strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>;
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}
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let isAsmParserOnly = 1 in {
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// Square root.
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let Predicates = [HasAVX, HasSSE2] in {
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defm VSQRT : sse2_fp_unop_s_avx<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
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VEX_4V;
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defm VSQRT : sse2_fp_unop_p<0x51, "vsqrt", fsqrt, int_x86_sse2_sqrt_pd>, VEX;
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}
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let Predicates = [HasAVX, HasSSE1] in {
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defm VSQRT : sse1_fp_unop_s_avx<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
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VEX_4V;
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defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt, int_x86_sse_sqrt_ps>, VEX;
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// Reciprocal approximations. Note that these typically require refinement
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// in order to obtain suitable precision.
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defm VRSQRT : sse1_fp_unop_s_avx<0x52, "rsqrt", X86frsqrt,
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int_x86_sse_rsqrt_ss>, VEX_4V;
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defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt, int_x86_sse_rsqrt_ps>,
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VEX;
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defm VRCP : sse1_fp_unop_s_avx<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
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VEX_4V;
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defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp, int_x86_sse_rcp_ps>,
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VEX;
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}
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}
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// Square root.
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defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
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sse1_fp_unop_p<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ps>,
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@ -10873,3 +10873,68 @@
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// CHECK: vcvtpd2ps %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xf9,0x5a,0xda]
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vcvtpd2ps %xmm2, %xmm3
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// CHECK: vsqrtpd %xmm1, %xmm2
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// CHECK: encoding: [0xc5,0xf9,0x51,0xd1]
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vsqrtpd %xmm1, %xmm2
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// CHECK: vsqrtpd (%eax), %xmm2
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// CHECK: encoding: [0xc5,0xf9,0x51,0x10]
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vsqrtpd (%eax), %xmm2
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// CHECK: vsqrtps %xmm1, %xmm2
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// CHECK: encoding: [0xc5,0xf8,0x51,0xd1]
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vsqrtps %xmm1, %xmm2
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// CHECK: vsqrtps (%eax), %xmm2
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// CHECK: encoding: [0xc5,0xf8,0x51,0x10]
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vsqrtps (%eax), %xmm2
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// CHECK: vsqrtsd %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xeb,0x51,0xd9]
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vsqrtsd %xmm1, %xmm2, %xmm3
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// CHECK: vsqrtsd (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xeb,0x51,0x18]
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vsqrtsd (%eax), %xmm2, %xmm3
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// CHECK: vsqrtss %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xea,0x51,0xd9]
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vsqrtss %xmm1, %xmm2, %xmm3
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// CHECK: vsqrtss (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xea,0x51,0x18]
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vsqrtss (%eax), %xmm2, %xmm3
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// CHECK: vrsqrtps %xmm1, %xmm2
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// CHECK: encoding: [0xc5,0xf8,0x52,0xd1]
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vrsqrtps %xmm1, %xmm2
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// CHECK: vrsqrtps (%eax), %xmm2
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// CHECK: encoding: [0xc5,0xf8,0x52,0x10]
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vrsqrtps (%eax), %xmm2
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// CHECK: vrsqrtss %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xea,0x52,0xd9]
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vrsqrtss %xmm1, %xmm2, %xmm3
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// CHECK: vrsqrtss (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xea,0x52,0x18]
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vrsqrtss (%eax), %xmm2, %xmm3
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// CHECK: vrcpps %xmm1, %xmm2
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// CHECK: encoding: [0xc5,0xf8,0x53,0xd1]
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vrcpps %xmm1, %xmm2
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// CHECK: vrcpps (%eax), %xmm2
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// CHECK: encoding: [0xc5,0xf8,0x53,0x10]
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vrcpps (%eax), %xmm2
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// CHECK: vrcpss %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xea,0x53,0xd9]
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vrcpss %xmm1, %xmm2, %xmm3
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// CHECK: vrcpss (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xea,0x53,0x18]
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vrcpss (%eax), %xmm2, %xmm3
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@ -922,3 +922,67 @@ pshufb CPI1_0(%rip), %xmm1
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// CHECK: encoding: [0xc4,0x41,0x79,0x5a,0xdc]
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vcvtpd2ps %xmm12, %xmm11
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// CHECK: vsqrtpd %xmm11, %xmm12
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// CHECK: encoding: [0xc4,0x41,0x79,0x51,0xe3]
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vsqrtpd %xmm11, %xmm12
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// CHECK: vsqrtpd (%rax), %xmm12
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// CHECK: encoding: [0xc5,0x79,0x51,0x20]
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vsqrtpd (%rax), %xmm12
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// CHECK: vsqrtps %xmm11, %xmm12
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// CHECK: encoding: [0xc4,0x41,0x78,0x51,0xe3]
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vsqrtps %xmm11, %xmm12
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// CHECK: vsqrtps (%rax), %xmm12
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// CHECK: encoding: [0xc5,0x78,0x51,0x20]
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vsqrtps (%rax), %xmm12
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// CHECK: vsqrtsd %xmm11, %xmm12, %xmm10
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// CHECK: encoding: [0xc4,0x41,0x1b,0x51,0xd3]
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vsqrtsd %xmm11, %xmm12, %xmm10
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// CHECK: vsqrtsd (%rax), %xmm12, %xmm10
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// CHECK: encoding: [0xc5,0x1b,0x51,0x10]
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vsqrtsd (%rax), %xmm12, %xmm10
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// CHECK: vsqrtss %xmm11, %xmm12, %xmm10
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// CHECK: encoding: [0xc4,0x41,0x1a,0x51,0xd3]
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vsqrtss %xmm11, %xmm12, %xmm10
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// CHECK: vsqrtss (%rax), %xmm12, %xmm10
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// CHECK: encoding: [0xc5,0x1a,0x51,0x10]
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vsqrtss (%rax), %xmm12, %xmm10
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// CHECK: vrsqrtps %xmm11, %xmm12
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// CHECK: encoding: [0xc4,0x41,0x78,0x52,0xe3]
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vrsqrtps %xmm11, %xmm12
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// CHECK: vrsqrtps (%rax), %xmm12
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// CHECK: encoding: [0xc5,0x78,0x52,0x20]
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vrsqrtps (%rax), %xmm12
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// CHECK: vrsqrtss %xmm11, %xmm12, %xmm10
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// CHECK: encoding: [0xc4,0x41,0x1a,0x52,0xd3]
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vrsqrtss %xmm11, %xmm12, %xmm10
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// CHECK: vrsqrtss (%rax), %xmm12, %xmm10
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// CHECK: encoding: [0xc5,0x1a,0x52,0x10]
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vrsqrtss (%rax), %xmm12, %xmm10
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// CHECK: vrcpps %xmm11, %xmm12
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// CHECK: encoding: [0xc4,0x41,0x78,0x53,0xe3]
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vrcpps %xmm11, %xmm12
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// CHECK: vrcpps (%rax), %xmm12
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// CHECK: encoding: [0xc5,0x78,0x53,0x20]
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vrcpps (%rax), %xmm12
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// CHECK: vrcpss %xmm11, %xmm12, %xmm10
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// CHECK: encoding: [0xc4,0x41,0x1a,0x53,0xd3]
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vrcpss %xmm11, %xmm12, %xmm10
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// CHECK: vrcpss (%rax), %xmm12, %xmm10
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// CHECK: encoding: [0xc5,0x1a,0x53,0x10]
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vrcpss (%rax), %xmm12, %xmm10
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