mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-01-08 04:11:27 +00:00
Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.
llvm-svn: 181624
This commit is contained in:
Jyotsna Verma
parent
4e52b3900b
commit
2dfc0b2d13
@ -126,9 +126,9 @@ def getPredNewOpcode : InstrMapping {
|
||||
def getNewValueOpcode : InstrMapping {
|
||||
let FilterClass = "NewValueRel";
|
||||
let RowFields = ["BaseOpcode", "PredSense", "PNewValue"];
|
||||
let ColFields = ["isNVStore"];
|
||||
let KeyCol = ["0"];
|
||||
let ValueCols = [["1"]];
|
||||
let ColFields = ["NValueST"];
|
||||
let KeyCol = ["false"];
|
||||
let ValueCols = [["true"]];
|
||||
}
|
||||
|
||||
def getBasedWithImmOffset : InstrMapping {
|
||||
|
||||
@ -174,30 +174,56 @@ void HexagonFrameLowering::emitEpilogue(MachineFunction &MF,
|
||||
MachineBasicBlock::iterator MBBI = prior(MBB.end());
|
||||
DebugLoc dl = MBBI->getDebugLoc();
|
||||
//
|
||||
// Only insert deallocframe if we need to.
|
||||
// Only insert deallocframe if we need to. Also at -O0. See comment
|
||||
// in emitPrologue above.
|
||||
//
|
||||
if (hasFP(MF)) {
|
||||
if (hasFP(MF) || MF.getTarget().getOptLevel() == CodeGenOpt::None) {
|
||||
MachineBasicBlock::iterator MBBI = prior(MBB.end());
|
||||
MachineBasicBlock::iterator MBBI_end = MBB.end();
|
||||
//
|
||||
// For Hexagon, we don't need the frame size.
|
||||
//
|
||||
MachineFrameInfo *MFI = MF.getFrameInfo();
|
||||
int NumBytes = (int) MFI->getStackSize();
|
||||
|
||||
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
|
||||
|
||||
// Handle EH_RETURN.
|
||||
if (MBBI->getOpcode() == Hexagon::EH_RETURN_JMPR) {
|
||||
MachineOperand &OffsetReg = MBBI->getOperand(0);
|
||||
assert(OffsetReg.isReg() && "Offset should be in register!");
|
||||
BuildMI(MBB, MBBI, dl, TII.get(Hexagon::DEALLOCFRAME));
|
||||
BuildMI(MBB, MBBI, dl, TII.get(Hexagon::ADD_rr),
|
||||
Hexagon::R29).addReg(Hexagon::R29).addReg(Hexagon::R28);
|
||||
return;
|
||||
}
|
||||
// Replace 'jumpr r31' instruction with dealloc_return for V4 and higher
|
||||
// versions.
|
||||
if (STI.hasV4TOps() && MBBI->getOpcode() == Hexagon::JMPret
|
||||
&& !DisableDeallocRet) {
|
||||
// Remove jumpr node.
|
||||
MBB.erase(MBBI);
|
||||
// Check for RESTORE_DEALLOC_RET_JMP_V4 call. Don't emit an extra DEALLOC
|
||||
// instruction if we encounter it.
|
||||
MachineBasicBlock::iterator BeforeJMPR =
|
||||
MBB.begin() == MBBI ? MBBI : prior(MBBI);
|
||||
if (BeforeJMPR != MBBI &&
|
||||
BeforeJMPR->getOpcode() == Hexagon::RESTORE_DEALLOC_RET_JMP_V4) {
|
||||
// Remove the JMPR node.
|
||||
MBB.erase(MBBI);
|
||||
return;
|
||||
}
|
||||
|
||||
// Add dealloc_return.
|
||||
BuildMI(MBB, MBBI_end, dl, TII.get(Hexagon::DEALLOC_RET_V4))
|
||||
.addImm(NumBytes);
|
||||
} else { // Add deallocframe for V2 and V3.
|
||||
BuildMI(MBB, MBBI, dl, TII.get(Hexagon::DEALLOCFRAME)).addImm(NumBytes);
|
||||
MachineInstrBuilder MIB =
|
||||
BuildMI(MBB, MBBI_end, dl, TII.get(Hexagon::DEALLOC_RET_V4));
|
||||
// Transfer the function live-out registers.
|
||||
MIB->copyImplicitOps(*MBB.getParent(), &*MBBI);
|
||||
// Remove the JUMPR node.
|
||||
MBB.erase(MBBI);
|
||||
} else { // Add deallocframe for V2 and V3, and V4 tail calls.
|
||||
// Check for RESTORE_DEALLOC_BEFORE_TAILCALL_V4. We don't need an extra
|
||||
// DEALLOCFRAME instruction after it.
|
||||
MachineBasicBlock::iterator Term = MBB.getFirstTerminator();
|
||||
MachineBasicBlock::iterator I =
|
||||
Term == MBB.begin() ? MBB.end() : prior(Term);
|
||||
if (I != MBB.end() &&
|
||||
I->getOpcode() == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4)
|
||||
return;
|
||||
|
||||
BuildMI(MBB, MBBI, dl, TII.get(Hexagon::DEALLOCFRAME));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -158,6 +158,7 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
|
||||
string CextOpcode = "";
|
||||
string PredSense = "";
|
||||
string PNewValue = "";
|
||||
string NValueST = ""; // Set to "true" for new-value stores.
|
||||
string InputType = ""; // Input is "imm" or "reg" type.
|
||||
string isMEMri = "false"; // Set to "true" for load/store with MEMri operand.
|
||||
string isFloat = "false"; // Set to "true" for the floating-point load/store.
|
||||
@ -166,6 +167,7 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
|
||||
let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"),
|
||||
"");
|
||||
let PNewValue = !if(isPredicatedNew, "new", "");
|
||||
let NValueST = !if(isNVStore, "true", "false");
|
||||
|
||||
// *** Must match MCTargetDesc/HexagonBaseInfo.h ***
|
||||
}
|
||||
|
||||
@ -630,111 +630,6 @@ bool HexagonInstrInfo::isBranch (const MachineInstr *MI) const {
|
||||
return MI->getDesc().isBranch();
|
||||
}
|
||||
|
||||
bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
|
||||
switch (MI->getOpcode()) {
|
||||
default: return false;
|
||||
// Store Byte
|
||||
case Hexagon::STrib_nv_V4:
|
||||
case Hexagon::STrib_indexed_nv_V4:
|
||||
case Hexagon::STrib_indexed_shl_nv_V4:
|
||||
case Hexagon::STrib_shl_nv_V4:
|
||||
case Hexagon::STb_GP_nv_V4:
|
||||
case Hexagon::POST_STbri_nv_V4:
|
||||
case Hexagon::STrib_cPt_nv_V4:
|
||||
case Hexagon::STrib_cdnPt_nv_V4:
|
||||
case Hexagon::STrib_cNotPt_nv_V4:
|
||||
case Hexagon::STrib_cdnNotPt_nv_V4:
|
||||
case Hexagon::STrib_indexed_cPt_nv_V4:
|
||||
case Hexagon::STrib_indexed_cdnPt_nv_V4:
|
||||
case Hexagon::STrib_indexed_cNotPt_nv_V4:
|
||||
case Hexagon::STrib_indexed_cdnNotPt_nv_V4:
|
||||
case Hexagon::STrib_indexed_shl_cPt_nv_V4:
|
||||
case Hexagon::STrib_indexed_shl_cdnPt_nv_V4:
|
||||
case Hexagon::STrib_indexed_shl_cNotPt_nv_V4:
|
||||
case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4:
|
||||
case Hexagon::POST_STbri_cPt_nv_V4:
|
||||
case Hexagon::POST_STbri_cdnPt_nv_V4:
|
||||
case Hexagon::POST_STbri_cNotPt_nv_V4:
|
||||
case Hexagon::POST_STbri_cdnNotPt_nv_V4:
|
||||
case Hexagon::STb_GP_cPt_nv_V4:
|
||||
case Hexagon::STb_GP_cNotPt_nv_V4:
|
||||
case Hexagon::STb_GP_cdnPt_nv_V4:
|
||||
case Hexagon::STb_GP_cdnNotPt_nv_V4:
|
||||
case Hexagon::STrib_abs_nv_V4:
|
||||
case Hexagon::STrib_abs_cPt_nv_V4:
|
||||
case Hexagon::STrib_abs_cdnPt_nv_V4:
|
||||
case Hexagon::STrib_abs_cNotPt_nv_V4:
|
||||
case Hexagon::STrib_abs_cdnNotPt_nv_V4:
|
||||
|
||||
// Store Halfword
|
||||
case Hexagon::STrih_nv_V4:
|
||||
case Hexagon::STrih_indexed_nv_V4:
|
||||
case Hexagon::STrih_indexed_shl_nv_V4:
|
||||
case Hexagon::STrih_shl_nv_V4:
|
||||
case Hexagon::STh_GP_nv_V4:
|
||||
case Hexagon::POST_SThri_nv_V4:
|
||||
case Hexagon::STrih_cPt_nv_V4:
|
||||
case Hexagon::STrih_cdnPt_nv_V4:
|
||||
case Hexagon::STrih_cNotPt_nv_V4:
|
||||
case Hexagon::STrih_cdnNotPt_nv_V4:
|
||||
case Hexagon::STrih_indexed_cPt_nv_V4:
|
||||
case Hexagon::STrih_indexed_cdnPt_nv_V4:
|
||||
case Hexagon::STrih_indexed_cNotPt_nv_V4:
|
||||
case Hexagon::STrih_indexed_cdnNotPt_nv_V4:
|
||||
case Hexagon::STrih_indexed_shl_cPt_nv_V4:
|
||||
case Hexagon::STrih_indexed_shl_cdnPt_nv_V4:
|
||||
case Hexagon::STrih_indexed_shl_cNotPt_nv_V4:
|
||||
case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4:
|
||||
case Hexagon::POST_SThri_cPt_nv_V4:
|
||||
case Hexagon::POST_SThri_cdnPt_nv_V4:
|
||||
case Hexagon::POST_SThri_cNotPt_nv_V4:
|
||||
case Hexagon::POST_SThri_cdnNotPt_nv_V4:
|
||||
case Hexagon::STh_GP_cPt_nv_V4:
|
||||
case Hexagon::STh_GP_cNotPt_nv_V4:
|
||||
case Hexagon::STh_GP_cdnPt_nv_V4:
|
||||
case Hexagon::STh_GP_cdnNotPt_nv_V4:
|
||||
case Hexagon::STrih_abs_nv_V4:
|
||||
case Hexagon::STrih_abs_cPt_nv_V4:
|
||||
case Hexagon::STrih_abs_cdnPt_nv_V4:
|
||||
case Hexagon::STrih_abs_cNotPt_nv_V4:
|
||||
case Hexagon::STrih_abs_cdnNotPt_nv_V4:
|
||||
|
||||
// Store Word
|
||||
case Hexagon::STriw_nv_V4:
|
||||
case Hexagon::STriw_indexed_nv_V4:
|
||||
case Hexagon::STriw_indexed_shl_nv_V4:
|
||||
case Hexagon::STriw_shl_nv_V4:
|
||||
case Hexagon::STw_GP_nv_V4:
|
||||
case Hexagon::POST_STwri_nv_V4:
|
||||
case Hexagon::STriw_cPt_nv_V4:
|
||||
case Hexagon::STriw_cdnPt_nv_V4:
|
||||
case Hexagon::STriw_cNotPt_nv_V4:
|
||||
case Hexagon::STriw_cdnNotPt_nv_V4:
|
||||
case Hexagon::STriw_indexed_cPt_nv_V4:
|
||||
case Hexagon::STriw_indexed_cdnPt_nv_V4:
|
||||
case Hexagon::STriw_indexed_cNotPt_nv_V4:
|
||||
case Hexagon::STriw_indexed_cdnNotPt_nv_V4:
|
||||
case Hexagon::STriw_indexed_shl_cPt_nv_V4:
|
||||
case Hexagon::STriw_indexed_shl_cdnPt_nv_V4:
|
||||
case Hexagon::STriw_indexed_shl_cNotPt_nv_V4:
|
||||
case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4:
|
||||
case Hexagon::POST_STwri_cPt_nv_V4:
|
||||
case Hexagon::POST_STwri_cdnPt_nv_V4:
|
||||
case Hexagon::POST_STwri_cNotPt_nv_V4:
|
||||
case Hexagon::POST_STwri_cdnNotPt_nv_V4:
|
||||
case Hexagon::STw_GP_cPt_nv_V4:
|
||||
case Hexagon::STw_GP_cNotPt_nv_V4:
|
||||
case Hexagon::STw_GP_cdnPt_nv_V4:
|
||||
case Hexagon::STw_GP_cdnNotPt_nv_V4:
|
||||
case Hexagon::STriw_abs_nv_V4:
|
||||
case Hexagon::STriw_abs_cPt_nv_V4:
|
||||
case Hexagon::STriw_abs_cdnPt_nv_V4:
|
||||
case Hexagon::STriw_abs_cNotPt_nv_V4:
|
||||
case Hexagon::STriw_abs_cdnNotPt_nv_V4:
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
|
||||
if (isNewValueJump(MI))
|
||||
return true;
|
||||
@ -862,6 +757,18 @@ unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
|
||||
}
|
||||
}
|
||||
|
||||
// New Value Store instructions.
|
||||
bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
|
||||
const uint64_t F = MI->getDesc().TSFlags;
|
||||
|
||||
return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
|
||||
}
|
||||
|
||||
bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
|
||||
const uint64_t F = get(Opcode).TSFlags;
|
||||
|
||||
return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
|
||||
}
|
||||
|
||||
int HexagonInstrInfo::
|
||||
getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
|
||||
@ -1304,6 +1211,8 @@ isValidAutoIncImm(const EVT VT, const int Offset) const {
|
||||
|
||||
bool HexagonInstrInfo::
|
||||
isMemOp(const MachineInstr *MI) const {
|
||||
// return MI->getDesc().mayLoad() && MI->getDesc().mayStore();
|
||||
|
||||
switch (MI->getOpcode())
|
||||
{
|
||||
default: return false;
|
||||
@ -1611,6 +1520,34 @@ bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const {
|
||||
(isPredicated(MI) && isPredicatedNew(MI)));
|
||||
}
|
||||
|
||||
// Return the new value instruction for a given store.
|
||||
int HexagonInstrInfo::GetDotNewOp(const MachineInstr* MI) const {
|
||||
int NVOpcode = Hexagon::getNewValueOpcode(MI->getOpcode());
|
||||
if (NVOpcode >= 0) // Valid new-value store instruction.
|
||||
return NVOpcode;
|
||||
|
||||
switch (MI->getOpcode()) {
|
||||
default: llvm_unreachable("Unknown .new type");
|
||||
// store new value byte
|
||||
case Hexagon::STrib_shl_V4:
|
||||
return Hexagon::STrib_shl_nv_V4;
|
||||
|
||||
case Hexagon::STrih_shl_V4:
|
||||
return Hexagon::STrih_shl_nv_V4;
|
||||
|
||||
case Hexagon::STriw_f:
|
||||
return Hexagon::STriw_nv_V4;
|
||||
|
||||
case Hexagon::STriw_indexed_f:
|
||||
return Hexagon::STriw_indexed_nv_V4;
|
||||
|
||||
case Hexagon::STriw_shl_V4:
|
||||
return Hexagon::STriw_shl_nv_V4;
|
||||
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
// Return .new predicate version for an instruction.
|
||||
int HexagonInstrInfo::GetDotNewPredOp(MachineInstr *MI,
|
||||
const MachineBranchProbabilityInfo
|
||||
|
||||
@ -185,6 +185,7 @@ public:
|
||||
bool isNewValueInst(const MachineInstr* MI) const;
|
||||
bool isNewValue(const MachineInstr* MI) const;
|
||||
bool isDotNewInst(const MachineInstr* MI) const;
|
||||
int GetDotNewOp(const MachineInstr* MI) const;
|
||||
int GetDotNewPredOp(MachineInstr *MI,
|
||||
const MachineBranchProbabilityInfo
|
||||
*MBPI) const;
|
||||
@ -194,6 +195,7 @@ public:
|
||||
bool isExtended(const MachineInstr* MI) const;
|
||||
bool isPostIncrement(const MachineInstr* MI) const;
|
||||
bool isNewValueStore(const MachineInstr* MI) const;
|
||||
bool isNewValueStore(unsigned Opcode) const;
|
||||
bool isNewValueJump(const MachineInstr* MI) const;
|
||||
bool isNewValueJumpCandidate(const MachineInstr *MI) const;
|
||||
|
||||
|
||||
@ -2564,8 +2564,9 @@ def NTSTBIT_ri : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
|
||||
//Deallocate frame and return.
|
||||
// dealloc_return
|
||||
let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicable = 1,
|
||||
Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
|
||||
def DEALLOC_RET_V4 : NVInst_V4<(outs), (ins i32imm:$amt1),
|
||||
Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1 in {
|
||||
let validSubTargets = HasV4SubT in
|
||||
def DEALLOC_RET_V4 : LD0Inst<(outs), (ins),
|
||||
"dealloc_return",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
@ -2574,9 +2575,10 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicable = 1,
|
||||
// Restore registers and dealloc return function call.
|
||||
let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
|
||||
Defs = [R29, R30, R31, PC] in {
|
||||
let validSubTargets = HasV4SubT in
|
||||
def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs),
|
||||
(ins calltarget:$dst),
|
||||
"jump $dst // Restore_and_dealloc_return",
|
||||
"jump $dst",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
}
|
||||
@ -2584,9 +2586,10 @@ let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
|
||||
// Restore registers and dealloc frame before a tail call.
|
||||
let isCall = 1, isBarrier = 1,
|
||||
Defs = [R29, R30, R31, PC] in {
|
||||
let validSubTargets = HasV4SubT in
|
||||
def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs),
|
||||
(ins calltarget:$dst),
|
||||
"call $dst // Restore_and_dealloc_before_tailcall",
|
||||
"call $dst",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
}
|
||||
@ -2603,10 +2606,11 @@ let isCall = 1, isBarrier = 1,
|
||||
|
||||
// if (Ps) dealloc_return
|
||||
let isReturn = 1, isTerminator = 1,
|
||||
Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
|
||||
Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1,
|
||||
isPredicated = 1 in {
|
||||
def DEALLOC_RET_cPt_V4 : NVInst_V4<(outs),
|
||||
(ins PredRegs:$src1, i32imm:$amt1),
|
||||
let validSubTargets = HasV4SubT in
|
||||
def DEALLOC_RET_cPt_V4 : LD0Inst<(outs),
|
||||
(ins PredRegs:$src1),
|
||||
"if ($src1) dealloc_return",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
@ -2614,10 +2618,10 @@ let isReturn = 1, isTerminator = 1,
|
||||
|
||||
// if (!Ps) dealloc_return
|
||||
let isReturn = 1, isTerminator = 1,
|
||||
Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
|
||||
isPredicated = 1 in {
|
||||
def DEALLOC_RET_cNotPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
|
||||
i32imm:$amt1),
|
||||
Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1,
|
||||
isPredicated = 1, isPredicatedFalse = 1 in {
|
||||
let validSubTargets = HasV4SubT in
|
||||
def DEALLOC_RET_cNotPt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
|
||||
"if (!$src1) dealloc_return",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
@ -2625,10 +2629,10 @@ let isReturn = 1, isTerminator = 1,
|
||||
|
||||
// if (Ps.new) dealloc_return:nt
|
||||
let isReturn = 1, isTerminator = 1,
|
||||
Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
|
||||
Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1,
|
||||
isPredicated = 1 in {
|
||||
def DEALLOC_RET_cdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
|
||||
i32imm:$amt1),
|
||||
let validSubTargets = HasV4SubT in
|
||||
def DEALLOC_RET_cdnPnt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
|
||||
"if ($src1.new) dealloc_return:nt",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
@ -2636,10 +2640,10 @@ let isReturn = 1, isTerminator = 1,
|
||||
|
||||
// if (!Ps.new) dealloc_return:nt
|
||||
let isReturn = 1, isTerminator = 1,
|
||||
Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
|
||||
isPredicated = 1 in {
|
||||
def DEALLOC_RET_cNotdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
|
||||
i32imm:$amt1),
|
||||
Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1,
|
||||
isPredicated = 1, isPredicatedFalse = 1 in {
|
||||
let validSubTargets = HasV4SubT in
|
||||
def DEALLOC_RET_cNotdnPnt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
|
||||
"if (!$src1.new) dealloc_return:nt",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
@ -2647,21 +2651,21 @@ let isReturn = 1, isTerminator = 1,
|
||||
|
||||
// if (Ps.new) dealloc_return:t
|
||||
let isReturn = 1, isTerminator = 1,
|
||||
Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
|
||||
Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1,
|
||||
isPredicated = 1 in {
|
||||
def DEALLOC_RET_cdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
|
||||
i32imm:$amt1),
|
||||
let validSubTargets = HasV4SubT in
|
||||
def DEALLOC_RET_cdnPt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
|
||||
"if ($src1.new) dealloc_return:t",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
}
|
||||
|
||||
// if (!Ps.new) dealloc_return:nt
|
||||
// if (!Ps.new) dealloc_return:nt
|
||||
let isReturn = 1, isTerminator = 1,
|
||||
Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
|
||||
isPredicated = 1 in {
|
||||
def DEALLOC_RET_cNotdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
|
||||
i32imm:$amt1),
|
||||
Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1,
|
||||
isPredicated = 1, isPredicatedFalse = 1 in {
|
||||
let validSubTargets = HasV4SubT in
|
||||
def DEALLOC_RET_cNotdnPt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
|
||||
"if (!$src1.new) dealloc_return:t",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
@ -3063,37 +3067,42 @@ def : Pat<(HexagonCONST32_GP tblockaddress:$src1),
|
||||
(TFRI_V4 tblockaddress:$src1)>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
|
||||
let isExtended = 1, opExtendable = 2, AddedComplexity=50,
|
||||
neverHasSideEffects = 1, isPredicated = 1, validSubTargets = HasV4SubT in
|
||||
def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, globaladdress:$src2),
|
||||
"if($src1) $dst = ##$src2",
|
||||
(ins PredRegs:$src1, s16Ext:$src2),
|
||||
"if($src1) $dst = #$src2",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
|
||||
let isExtended = 1, opExtendable = 2, AddedComplexity=50, isPredicatedFalse = 1,
|
||||
neverHasSideEffects = 1, isPredicated = 1, validSubTargets = HasV4SubT in
|
||||
def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, globaladdress:$src2),
|
||||
"if(!$src1) $dst = ##$src2",
|
||||
(ins PredRegs:$src1, s16Ext:$src2),
|
||||
"if(!$src1) $dst = #$src2",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
|
||||
let isExtended = 1, opExtendable = 2, AddedComplexity=50,
|
||||
neverHasSideEffects = 1, isPredicated = 1, validSubTargets = HasV4SubT in
|
||||
def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, globaladdress:$src2),
|
||||
"if($src1.new) $dst = ##$src2",
|
||||
(ins PredRegs:$src1, s16Ext:$src2),
|
||||
"if($src1.new) $dst = #$src2",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
|
||||
let isExtended = 1, opExtendable = 2, AddedComplexity=50, isPredicatedFalse = 1,
|
||||
neverHasSideEffects = 1, isPredicated = 1, validSubTargets = HasV4SubT in
|
||||
def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, globaladdress:$src2),
|
||||
"if(!$src1.new) $dst = ##$src2",
|
||||
(ins PredRegs:$src1, s16Ext:$src2),
|
||||
"if(!$src1.new) $dst = #$src2",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let AddedComplexity = 50, Predicates = [HasV4T] in
|
||||
def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
|
||||
(TFRI_V4 tglobaladdr:$src1)>;
|
||||
(TFRI_V4 tglobaladdr:$src1)>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
|
||||
// Load - Indirect with long offset: These instructions take global address
|
||||
|
||||
@ -26,22 +26,29 @@ def CONST32_Float_Real : LDInst<(outs IntRegs:$dst), (ins f32imm:$src1),
|
||||
// Only works with single precision fp value.
|
||||
// For double precision, use CONST64_float_real, as 64bit transfer
|
||||
// can only hold 40-bit values - 32 from const ext + 8 bit immediate.
|
||||
let isMoveImm = 1, isReMaterializable = 1, isPredicable = 1 in
|
||||
def TFRI_f : ALU32_ri<(outs IntRegs:$dst), (ins f32imm:$src1),
|
||||
"$dst = ##$src1",
|
||||
// Make sure that complexity is more than the CONST32 pattern in
|
||||
// HexagonInstrInfo.td patterns.
|
||||
let isExtended = 1, opExtendable = 1, isMoveImm = 1, isReMaterializable = 1,
|
||||
isPredicable = 1, AddedComplexity = 30, validSubTargets = HasV5SubT,
|
||||
isCodeGenOnly = 1 in
|
||||
def TFRI_f : ALU32_ri<(outs IntRegs:$dst), (ins f32Ext:$src1),
|
||||
"$dst = #$src1",
|
||||
[(set IntRegs:$dst, fpimm:$src1)]>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
let isExtended = 1, opExtendable = 2, isPredicated = 1,
|
||||
neverHasSideEffects = 1, validSubTargets = HasV5SubT in
|
||||
def TFRI_cPt_f : ALU32_ri<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, f32imm:$src2),
|
||||
"if ($src1) $dst = ##$src2",
|
||||
(ins PredRegs:$src1, f32Ext:$src2),
|
||||
"if ($src1) $dst = #$src2",
|
||||
[]>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
let isExtended = 1, opExtendable = 2, isPredicated = 1, isPredicatedFalse = 1,
|
||||
neverHasSideEffects = 1, validSubTargets = HasV5SubT in
|
||||
def TFRI_cNotPt_f : ALU32_ri<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, f32imm:$src2),
|
||||
"if (!$src1) $dst = ##$src2",
|
||||
(ins PredRegs:$src1, f32Ext:$src2),
|
||||
"if (!$src1) $dst =#$src2",
|
||||
[]>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
|
||||
@ -498,250 +498,6 @@ static bool DoesModifyCalleeSavedReg(MachineInstr *MI,
|
||||
return false;
|
||||
}
|
||||
|
||||
// Return the new value instruction for a given store.
|
||||
static int GetDotNewOp(const int opc) {
|
||||
switch (opc) {
|
||||
default: llvm_unreachable("Unknown .new type");
|
||||
// store new value byte
|
||||
case Hexagon::STrib:
|
||||
return Hexagon::STrib_nv_V4;
|
||||
|
||||
case Hexagon::STrib_indexed:
|
||||
return Hexagon::STrib_indexed_nv_V4;
|
||||
|
||||
case Hexagon::STrib_indexed_shl_V4:
|
||||
return Hexagon::STrib_indexed_shl_nv_V4;
|
||||
|
||||
case Hexagon::STrib_shl_V4:
|
||||
return Hexagon::STrib_shl_nv_V4;
|
||||
|
||||
case Hexagon::STb_GP_V4:
|
||||
return Hexagon::STb_GP_nv_V4;
|
||||
|
||||
case Hexagon::POST_STbri:
|
||||
return Hexagon::POST_STbri_nv_V4;
|
||||
|
||||
case Hexagon::STrib_cPt:
|
||||
return Hexagon::STrib_cPt_nv_V4;
|
||||
|
||||
case Hexagon::STrib_cdnPt_V4:
|
||||
return Hexagon::STrib_cdnPt_nv_V4;
|
||||
|
||||
case Hexagon::STrib_cNotPt:
|
||||
return Hexagon::STrib_cNotPt_nv_V4;
|
||||
|
||||
case Hexagon::STrib_cdnNotPt_V4:
|
||||
return Hexagon::STrib_cdnNotPt_nv_V4;
|
||||
|
||||
case Hexagon::STrib_indexed_cPt:
|
||||
return Hexagon::STrib_indexed_cPt_nv_V4;
|
||||
|
||||
case Hexagon::STrib_indexed_cdnPt_V4:
|
||||
return Hexagon::STrib_indexed_cdnPt_nv_V4;
|
||||
|
||||
case Hexagon::STrib_indexed_cNotPt:
|
||||
return Hexagon::STrib_indexed_cNotPt_nv_V4;
|
||||
|
||||
case Hexagon::STrib_indexed_cdnNotPt_V4:
|
||||
return Hexagon::STrib_indexed_cdnNotPt_nv_V4;
|
||||
|
||||
case Hexagon::STrib_indexed_shl_cPt_V4:
|
||||
return Hexagon::STrib_indexed_shl_cPt_nv_V4;
|
||||
|
||||
case Hexagon::STrib_indexed_shl_cdnPt_V4:
|
||||
return Hexagon::STrib_indexed_shl_cdnPt_nv_V4;
|
||||
|
||||
case Hexagon::STrib_indexed_shl_cNotPt_V4:
|
||||
return Hexagon::STrib_indexed_shl_cNotPt_nv_V4;
|
||||
|
||||
case Hexagon::STrib_indexed_shl_cdnNotPt_V4:
|
||||
return Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4;
|
||||
|
||||
case Hexagon::POST_STbri_cPt:
|
||||
return Hexagon::POST_STbri_cPt_nv_V4;
|
||||
|
||||
case Hexagon::POST_STbri_cdnPt_V4:
|
||||
return Hexagon::POST_STbri_cdnPt_nv_V4;
|
||||
|
||||
case Hexagon::POST_STbri_cNotPt:
|
||||
return Hexagon::POST_STbri_cNotPt_nv_V4;
|
||||
|
||||
case Hexagon::POST_STbri_cdnNotPt_V4:
|
||||
return Hexagon::POST_STbri_cdnNotPt_nv_V4;
|
||||
|
||||
case Hexagon::STb_GP_cPt_V4:
|
||||
return Hexagon::STb_GP_cPt_nv_V4;
|
||||
|
||||
case Hexagon::STb_GP_cNotPt_V4:
|
||||
return Hexagon::STb_GP_cNotPt_nv_V4;
|
||||
|
||||
case Hexagon::STb_GP_cdnPt_V4:
|
||||
return Hexagon::STb_GP_cdnPt_nv_V4;
|
||||
|
||||
case Hexagon::STb_GP_cdnNotPt_V4:
|
||||
return Hexagon::STb_GP_cdnNotPt_nv_V4;
|
||||
|
||||
// store new value halfword
|
||||
case Hexagon::STrih:
|
||||
return Hexagon::STrih_nv_V4;
|
||||
|
||||
case Hexagon::STrih_indexed:
|
||||
return Hexagon::STrih_indexed_nv_V4;
|
||||
|
||||
case Hexagon::STrih_indexed_shl_V4:
|
||||
return Hexagon::STrih_indexed_shl_nv_V4;
|
||||
|
||||
case Hexagon::STrih_shl_V4:
|
||||
return Hexagon::STrih_shl_nv_V4;
|
||||
|
||||
case Hexagon::STh_GP_V4:
|
||||
return Hexagon::STh_GP_nv_V4;
|
||||
|
||||
case Hexagon::POST_SThri:
|
||||
return Hexagon::POST_SThri_nv_V4;
|
||||
|
||||
case Hexagon::STrih_cPt:
|
||||
return Hexagon::STrih_cPt_nv_V4;
|
||||
|
||||
case Hexagon::STrih_cdnPt_V4:
|
||||
return Hexagon::STrih_cdnPt_nv_V4;
|
||||
|
||||
case Hexagon::STrih_cNotPt:
|
||||
return Hexagon::STrih_cNotPt_nv_V4;
|
||||
|
||||
case Hexagon::STrih_cdnNotPt_V4:
|
||||
return Hexagon::STrih_cdnNotPt_nv_V4;
|
||||
|
||||
case Hexagon::STrih_indexed_cPt:
|
||||
return Hexagon::STrih_indexed_cPt_nv_V4;
|
||||
|
||||
case Hexagon::STrih_indexed_cdnPt_V4:
|
||||
return Hexagon::STrih_indexed_cdnPt_nv_V4;
|
||||
|
||||
case Hexagon::STrih_indexed_cNotPt:
|
||||
return Hexagon::STrih_indexed_cNotPt_nv_V4;
|
||||
|
||||
case Hexagon::STrih_indexed_cdnNotPt_V4:
|
||||
return Hexagon::STrih_indexed_cdnNotPt_nv_V4;
|
||||
|
||||
case Hexagon::STrih_indexed_shl_cPt_V4:
|
||||
return Hexagon::STrih_indexed_shl_cPt_nv_V4;
|
||||
|
||||
case Hexagon::STrih_indexed_shl_cdnPt_V4:
|
||||
return Hexagon::STrih_indexed_shl_cdnPt_nv_V4;
|
||||
|
||||
case Hexagon::STrih_indexed_shl_cNotPt_V4:
|
||||
return Hexagon::STrih_indexed_shl_cNotPt_nv_V4;
|
||||
|
||||
case Hexagon::STrih_indexed_shl_cdnNotPt_V4:
|
||||
return Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4;
|
||||
|
||||
case Hexagon::POST_SThri_cPt:
|
||||
return Hexagon::POST_SThri_cPt_nv_V4;
|
||||
|
||||
case Hexagon::POST_SThri_cdnPt_V4:
|
||||
return Hexagon::POST_SThri_cdnPt_nv_V4;
|
||||
|
||||
case Hexagon::POST_SThri_cNotPt:
|
||||
return Hexagon::POST_SThri_cNotPt_nv_V4;
|
||||
|
||||
case Hexagon::POST_SThri_cdnNotPt_V4:
|
||||
return Hexagon::POST_SThri_cdnNotPt_nv_V4;
|
||||
|
||||
case Hexagon::STh_GP_cPt_V4:
|
||||
return Hexagon::STh_GP_cPt_nv_V4;
|
||||
|
||||
case Hexagon::STh_GP_cNotPt_V4:
|
||||
return Hexagon::STh_GP_cNotPt_nv_V4;
|
||||
|
||||
case Hexagon::STh_GP_cdnPt_V4:
|
||||
return Hexagon::STh_GP_cdnPt_nv_V4;
|
||||
|
||||
case Hexagon::STh_GP_cdnNotPt_V4:
|
||||
return Hexagon::STh_GP_cdnNotPt_nv_V4;
|
||||
|
||||
// store new value word
|
||||
case Hexagon::STriw:
|
||||
return Hexagon::STriw_nv_V4;
|
||||
|
||||
case Hexagon::STriw_indexed:
|
||||
return Hexagon::STriw_indexed_nv_V4;
|
||||
|
||||
case Hexagon::STriw_indexed_shl_V4:
|
||||
return Hexagon::STriw_indexed_shl_nv_V4;
|
||||
|
||||
case Hexagon::STriw_shl_V4:
|
||||
return Hexagon::STriw_shl_nv_V4;
|
||||
|
||||
case Hexagon::STw_GP_V4:
|
||||
return Hexagon::STw_GP_nv_V4;
|
||||
|
||||
case Hexagon::POST_STwri:
|
||||
return Hexagon::POST_STwri_nv_V4;
|
||||
|
||||
case Hexagon::STriw_cPt:
|
||||
return Hexagon::STriw_cPt_nv_V4;
|
||||
|
||||
case Hexagon::STriw_cdnPt_V4:
|
||||
return Hexagon::STriw_cdnPt_nv_V4;
|
||||
|
||||
case Hexagon::STriw_cNotPt:
|
||||
return Hexagon::STriw_cNotPt_nv_V4;
|
||||
|
||||
case Hexagon::STriw_cdnNotPt_V4:
|
||||
return Hexagon::STriw_cdnNotPt_nv_V4;
|
||||
|
||||
case Hexagon::STriw_indexed_cPt:
|
||||
return Hexagon::STriw_indexed_cPt_nv_V4;
|
||||
|
||||
case Hexagon::STriw_indexed_cdnPt_V4:
|
||||
return Hexagon::STriw_indexed_cdnPt_nv_V4;
|
||||
|
||||
case Hexagon::STriw_indexed_cNotPt:
|
||||
return Hexagon::STriw_indexed_cNotPt_nv_V4;
|
||||
|
||||
case Hexagon::STriw_indexed_cdnNotPt_V4:
|
||||
return Hexagon::STriw_indexed_cdnNotPt_nv_V4;
|
||||
|
||||
case Hexagon::STriw_indexed_shl_cPt_V4:
|
||||
return Hexagon::STriw_indexed_shl_cPt_nv_V4;
|
||||
|
||||
case Hexagon::STriw_indexed_shl_cdnPt_V4:
|
||||
return Hexagon::STriw_indexed_shl_cdnPt_nv_V4;
|
||||
|
||||
case Hexagon::STriw_indexed_shl_cNotPt_V4:
|
||||
return Hexagon::STriw_indexed_shl_cNotPt_nv_V4;
|
||||
|
||||
case Hexagon::STriw_indexed_shl_cdnNotPt_V4:
|
||||
return Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4;
|
||||
|
||||
case Hexagon::POST_STwri_cPt:
|
||||
return Hexagon::POST_STwri_cPt_nv_V4;
|
||||
|
||||
case Hexagon::POST_STwri_cdnPt_V4:
|
||||
return Hexagon::POST_STwri_cdnPt_nv_V4;
|
||||
|
||||
case Hexagon::POST_STwri_cNotPt:
|
||||
return Hexagon::POST_STwri_cNotPt_nv_V4;
|
||||
|
||||
case Hexagon::POST_STwri_cdnNotPt_V4:
|
||||
return Hexagon::POST_STwri_cdnNotPt_nv_V4;
|
||||
|
||||
case Hexagon::STw_GP_cPt_V4:
|
||||
return Hexagon::STw_GP_cPt_nv_V4;
|
||||
|
||||
case Hexagon::STw_GP_cNotPt_V4:
|
||||
return Hexagon::STw_GP_cNotPt_nv_V4;
|
||||
|
||||
case Hexagon::STw_GP_cdnPt_V4:
|
||||
return Hexagon::STw_GP_cdnPt_nv_V4;
|
||||
|
||||
case Hexagon::STw_GP_cdnNotPt_V4:
|
||||
return Hexagon::STw_GP_cdnNotPt_nv_V4;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
// Returns true if an instruction can be promoted to .new predicate
|
||||
// or new-value store.
|
||||
bool HexagonPacketizerList::isNewifiable(MachineInstr* MI) {
|
||||
@ -781,7 +537,7 @@ bool HexagonPacketizerList::PromoteToDotNew(MachineInstr* MI,
|
||||
if (RC == &Hexagon::PredRegsRegClass)
|
||||
NewOpcode = QII->GetDotNewPredOp(MI, MBPI);
|
||||
else
|
||||
NewOpcode = GetDotNewOp(MI->getOpcode());
|
||||
NewOpcode = QII->GetDotNewOp(MI);
|
||||
MI->setDesc(QII->get(NewOpcode));
|
||||
|
||||
return true;
|
||||
@ -1380,295 +1136,23 @@ bool HexagonPacketizerList::DemoteToDotOld(MachineInstr* MI) {
|
||||
return true;
|
||||
}
|
||||
|
||||
// Returns true if an instruction is predicated on p0 and false if it's
|
||||
// predicated on !p0.
|
||||
enum PredicateKind {
|
||||
PK_False,
|
||||
PK_True,
|
||||
PK_Unknown
|
||||
};
|
||||
|
||||
static bool GetPredicateSense(MachineInstr* MI,
|
||||
const HexagonInstrInfo *QII) {
|
||||
/// Returns true if an instruction is predicated on p0 and false if it's
|
||||
/// predicated on !p0.
|
||||
static PredicateKind getPredicateSense(MachineInstr* MI,
|
||||
const HexagonInstrInfo *QII) {
|
||||
if (!QII->isPredicated(MI))
|
||||
return PK_Unknown;
|
||||
|
||||
switch (MI->getOpcode()) {
|
||||
default: llvm_unreachable("Unknown predicate sense of the instruction");
|
||||
case Hexagon::TFR_cPt:
|
||||
case Hexagon::TFR_cdnPt:
|
||||
case Hexagon::TFRI_cPt:
|
||||
case Hexagon::TFRI_cdnPt:
|
||||
case Hexagon::STrib_cPt :
|
||||
case Hexagon::STrib_cdnPt_V4 :
|
||||
case Hexagon::STrib_indexed_cPt :
|
||||
case Hexagon::STrib_indexed_cdnPt_V4 :
|
||||
case Hexagon::STrib_indexed_shl_cPt_V4 :
|
||||
case Hexagon::STrib_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::POST_STbri_cPt :
|
||||
case Hexagon::POST_STbri_cdnPt_V4 :
|
||||
case Hexagon::STrih_cPt :
|
||||
case Hexagon::STrih_cdnPt_V4 :
|
||||
case Hexagon::STrih_indexed_cPt :
|
||||
case Hexagon::STrih_indexed_cdnPt_V4 :
|
||||
case Hexagon::STrih_indexed_shl_cPt_V4 :
|
||||
case Hexagon::STrih_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::POST_SThri_cPt :
|
||||
case Hexagon::POST_SThri_cdnPt_V4 :
|
||||
case Hexagon::STriw_cPt :
|
||||
case Hexagon::STriw_cdnPt_V4 :
|
||||
case Hexagon::STriw_indexed_cPt :
|
||||
case Hexagon::STriw_indexed_cdnPt_V4 :
|
||||
case Hexagon::STriw_indexed_shl_cPt_V4 :
|
||||
case Hexagon::STriw_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::POST_STwri_cPt :
|
||||
case Hexagon::POST_STwri_cdnPt_V4 :
|
||||
case Hexagon::STrib_imm_cPt_V4 :
|
||||
case Hexagon::STrib_imm_cdnPt_V4 :
|
||||
case Hexagon::STrid_cPt :
|
||||
case Hexagon::STrid_cdnPt_V4 :
|
||||
case Hexagon::STrid_indexed_cPt :
|
||||
case Hexagon::STrid_indexed_cdnPt_V4 :
|
||||
case Hexagon::STrid_indexed_shl_cPt_V4 :
|
||||
case Hexagon::STrid_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::POST_STdri_cPt :
|
||||
case Hexagon::POST_STdri_cdnPt_V4 :
|
||||
case Hexagon::STrih_imm_cPt_V4 :
|
||||
case Hexagon::STrih_imm_cdnPt_V4 :
|
||||
case Hexagon::STriw_imm_cPt_V4 :
|
||||
case Hexagon::STriw_imm_cdnPt_V4 :
|
||||
case Hexagon::JMP_tnew_t :
|
||||
case Hexagon::LDrid_cPt :
|
||||
case Hexagon::LDrid_cdnPt :
|
||||
case Hexagon::LDrid_indexed_cPt :
|
||||
case Hexagon::LDrid_indexed_cdnPt :
|
||||
case Hexagon::POST_LDrid_cPt :
|
||||
case Hexagon::POST_LDrid_cdnPt_V4 :
|
||||
case Hexagon::LDriw_cPt :
|
||||
case Hexagon::LDriw_cdnPt :
|
||||
case Hexagon::LDriw_indexed_cPt :
|
||||
case Hexagon::LDriw_indexed_cdnPt :
|
||||
case Hexagon::POST_LDriw_cPt :
|
||||
case Hexagon::POST_LDriw_cdnPt_V4 :
|
||||
case Hexagon::LDrih_cPt :
|
||||
case Hexagon::LDrih_cdnPt :
|
||||
case Hexagon::LDrih_indexed_cPt :
|
||||
case Hexagon::LDrih_indexed_cdnPt :
|
||||
case Hexagon::POST_LDrih_cPt :
|
||||
case Hexagon::POST_LDrih_cdnPt_V4 :
|
||||
case Hexagon::LDrib_cPt :
|
||||
case Hexagon::LDrib_cdnPt :
|
||||
case Hexagon::LDrib_indexed_cPt :
|
||||
case Hexagon::LDrib_indexed_cdnPt :
|
||||
case Hexagon::POST_LDrib_cPt :
|
||||
case Hexagon::POST_LDrib_cdnPt_V4 :
|
||||
case Hexagon::LDriuh_cPt :
|
||||
case Hexagon::LDriuh_cdnPt :
|
||||
case Hexagon::LDriuh_indexed_cPt :
|
||||
case Hexagon::LDriuh_indexed_cdnPt :
|
||||
case Hexagon::POST_LDriuh_cPt :
|
||||
case Hexagon::POST_LDriuh_cdnPt_V4 :
|
||||
case Hexagon::LDriub_cPt :
|
||||
case Hexagon::LDriub_cdnPt :
|
||||
case Hexagon::LDriub_indexed_cPt :
|
||||
case Hexagon::LDriub_indexed_cdnPt :
|
||||
case Hexagon::POST_LDriub_cPt :
|
||||
case Hexagon::POST_LDriub_cdnPt_V4 :
|
||||
case Hexagon::LDrid_indexed_shl_cPt_V4 :
|
||||
case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::LDrib_indexed_shl_cPt_V4 :
|
||||
case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::LDriub_indexed_shl_cPt_V4 :
|
||||
case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::LDrih_indexed_shl_cPt_V4 :
|
||||
case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::LDriuh_indexed_shl_cPt_V4 :
|
||||
case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::LDriw_indexed_shl_cPt_V4 :
|
||||
case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::ADD_ri_cPt :
|
||||
case Hexagon::ADD_ri_cdnPt :
|
||||
case Hexagon::ADD_rr_cPt :
|
||||
case Hexagon::ADD_rr_cdnPt :
|
||||
case Hexagon::XOR_rr_cPt :
|
||||
case Hexagon::XOR_rr_cdnPt :
|
||||
case Hexagon::AND_rr_cPt :
|
||||
case Hexagon::AND_rr_cdnPt :
|
||||
case Hexagon::OR_rr_cPt :
|
||||
case Hexagon::OR_rr_cdnPt :
|
||||
case Hexagon::SUB_rr_cPt :
|
||||
case Hexagon::SUB_rr_cdnPt :
|
||||
case Hexagon::COMBINE_rr_cPt :
|
||||
case Hexagon::COMBINE_rr_cdnPt :
|
||||
case Hexagon::ASLH_cPt_V4 :
|
||||
case Hexagon::ASLH_cdnPt_V4 :
|
||||
case Hexagon::ASRH_cPt_V4 :
|
||||
case Hexagon::ASRH_cdnPt_V4 :
|
||||
case Hexagon::SXTB_cPt_V4 :
|
||||
case Hexagon::SXTB_cdnPt_V4 :
|
||||
case Hexagon::SXTH_cPt_V4 :
|
||||
case Hexagon::SXTH_cdnPt_V4 :
|
||||
case Hexagon::ZXTB_cPt_V4 :
|
||||
case Hexagon::ZXTB_cdnPt_V4 :
|
||||
case Hexagon::ZXTH_cPt_V4 :
|
||||
case Hexagon::ZXTH_cdnPt_V4 :
|
||||
case Hexagon::LDd_GP_cPt_V4 :
|
||||
case Hexagon::LDb_GP_cPt_V4 :
|
||||
case Hexagon::LDub_GP_cPt_V4 :
|
||||
case Hexagon::LDh_GP_cPt_V4 :
|
||||
case Hexagon::LDuh_GP_cPt_V4 :
|
||||
case Hexagon::LDw_GP_cPt_V4 :
|
||||
case Hexagon::STd_GP_cPt_V4 :
|
||||
case Hexagon::STb_GP_cPt_V4 :
|
||||
case Hexagon::STh_GP_cPt_V4 :
|
||||
case Hexagon::STw_GP_cPt_V4 :
|
||||
case Hexagon::LDd_GP_cdnPt_V4 :
|
||||
case Hexagon::LDb_GP_cdnPt_V4 :
|
||||
case Hexagon::LDub_GP_cdnPt_V4 :
|
||||
case Hexagon::LDh_GP_cdnPt_V4 :
|
||||
case Hexagon::LDuh_GP_cdnPt_V4 :
|
||||
case Hexagon::LDw_GP_cdnPt_V4 :
|
||||
case Hexagon::STd_GP_cdnPt_V4 :
|
||||
case Hexagon::STb_GP_cdnPt_V4 :
|
||||
case Hexagon::STh_GP_cdnPt_V4 :
|
||||
case Hexagon::STw_GP_cdnPt_V4 :
|
||||
return true;
|
||||
if (QII->isPredicatedTrue(MI))
|
||||
return PK_True;
|
||||
|
||||
case Hexagon::TFR_cNotPt:
|
||||
case Hexagon::TFR_cdnNotPt:
|
||||
case Hexagon::TFRI_cNotPt:
|
||||
case Hexagon::TFRI_cdnNotPt:
|
||||
case Hexagon::STrib_cNotPt :
|
||||
case Hexagon::STrib_cdnNotPt_V4 :
|
||||
case Hexagon::STrib_indexed_cNotPt :
|
||||
case Hexagon::STrib_indexed_cdnNotPt_V4 :
|
||||
case Hexagon::STrib_indexed_shl_cNotPt_V4 :
|
||||
case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
|
||||
case Hexagon::POST_STbri_cNotPt :
|
||||
case Hexagon::POST_STbri_cdnNotPt_V4 :
|
||||
case Hexagon::STrih_cNotPt :
|
||||
case Hexagon::STrih_cdnNotPt_V4 :
|
||||
case Hexagon::STrih_indexed_cNotPt :
|
||||
case Hexagon::STrih_indexed_cdnNotPt_V4 :
|
||||
case Hexagon::STrih_indexed_shl_cNotPt_V4 :
|
||||
case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
|
||||
case Hexagon::POST_SThri_cNotPt :
|
||||
case Hexagon::POST_SThri_cdnNotPt_V4 :
|
||||
case Hexagon::STriw_cNotPt :
|
||||
case Hexagon::STriw_cdnNotPt_V4 :
|
||||
case Hexagon::STriw_indexed_cNotPt :
|
||||
case Hexagon::STriw_indexed_cdnNotPt_V4 :
|
||||
case Hexagon::STriw_indexed_shl_cNotPt_V4 :
|
||||
case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
|
||||
case Hexagon::POST_STwri_cNotPt :
|
||||
case Hexagon::POST_STwri_cdnNotPt_V4 :
|
||||
case Hexagon::STrib_imm_cNotPt_V4 :
|
||||
case Hexagon::STrib_imm_cdnNotPt_V4 :
|
||||
case Hexagon::STrid_cNotPt :
|
||||
case Hexagon::STrid_cdnNotPt_V4 :
|
||||
case Hexagon::STrid_indexed_cdnNotPt_V4 :
|
||||
case Hexagon::STrid_indexed_cNotPt :
|
||||
case Hexagon::STrid_indexed_shl_cNotPt_V4 :
|
||||
case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
|
||||
case Hexagon::POST_STdri_cNotPt :
|
||||
case Hexagon::POST_STdri_cdnNotPt_V4 :
|
||||
case Hexagon::STrih_imm_cNotPt_V4 :
|
||||
case Hexagon::STrih_imm_cdnNotPt_V4 :
|
||||
case Hexagon::STriw_imm_cNotPt_V4 :
|
||||
case Hexagon::STriw_imm_cdnNotPt_V4 :
|
||||
case Hexagon::JMP_fnew_t :
|
||||
case Hexagon::LDrid_cNotPt :
|
||||
case Hexagon::LDrid_cdnNotPt :
|
||||
case Hexagon::LDrid_indexed_cNotPt :
|
||||
case Hexagon::LDrid_indexed_cdnNotPt :
|
||||
case Hexagon::POST_LDrid_cNotPt :
|
||||
case Hexagon::POST_LDrid_cdnNotPt_V4 :
|
||||
case Hexagon::LDriw_cNotPt :
|
||||
case Hexagon::LDriw_cdnNotPt :
|
||||
case Hexagon::LDriw_indexed_cNotPt :
|
||||
case Hexagon::LDriw_indexed_cdnNotPt :
|
||||
case Hexagon::POST_LDriw_cNotPt :
|
||||
case Hexagon::POST_LDriw_cdnNotPt_V4 :
|
||||
case Hexagon::LDrih_cNotPt :
|
||||
case Hexagon::LDrih_cdnNotPt :
|
||||
case Hexagon::LDrih_indexed_cNotPt :
|
||||
case Hexagon::LDrih_indexed_cdnNotPt :
|
||||
case Hexagon::POST_LDrih_cNotPt :
|
||||
case Hexagon::POST_LDrih_cdnNotPt_V4 :
|
||||
case Hexagon::LDrib_cNotPt :
|
||||
case Hexagon::LDrib_cdnNotPt :
|
||||
case Hexagon::LDrib_indexed_cNotPt :
|
||||
case Hexagon::LDrib_indexed_cdnNotPt :
|
||||
case Hexagon::POST_LDrib_cNotPt :
|
||||
case Hexagon::POST_LDrib_cdnNotPt_V4 :
|
||||
case Hexagon::LDriuh_cNotPt :
|
||||
case Hexagon::LDriuh_cdnNotPt :
|
||||
case Hexagon::LDriuh_indexed_cNotPt :
|
||||
case Hexagon::LDriuh_indexed_cdnNotPt :
|
||||
case Hexagon::POST_LDriuh_cNotPt :
|
||||
case Hexagon::POST_LDriuh_cdnNotPt_V4 :
|
||||
case Hexagon::LDriub_cNotPt :
|
||||
case Hexagon::LDriub_cdnNotPt :
|
||||
case Hexagon::LDriub_indexed_cNotPt :
|
||||
case Hexagon::LDriub_indexed_cdnNotPt :
|
||||
case Hexagon::POST_LDriub_cNotPt :
|
||||
case Hexagon::POST_LDriub_cdnNotPt_V4 :
|
||||
case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
|
||||
case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
|
||||
case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
|
||||
case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
|
||||
case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
|
||||
case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
|
||||
case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
|
||||
case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
|
||||
case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
|
||||
case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
|
||||
case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
|
||||
case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
|
||||
case Hexagon::ADD_ri_cNotPt :
|
||||
case Hexagon::ADD_ri_cdnNotPt :
|
||||
case Hexagon::ADD_rr_cNotPt :
|
||||
case Hexagon::ADD_rr_cdnNotPt :
|
||||
case Hexagon::XOR_rr_cNotPt :
|
||||
case Hexagon::XOR_rr_cdnNotPt :
|
||||
case Hexagon::AND_rr_cNotPt :
|
||||
case Hexagon::AND_rr_cdnNotPt :
|
||||
case Hexagon::OR_rr_cNotPt :
|
||||
case Hexagon::OR_rr_cdnNotPt :
|
||||
case Hexagon::SUB_rr_cNotPt :
|
||||
case Hexagon::SUB_rr_cdnNotPt :
|
||||
case Hexagon::COMBINE_rr_cNotPt :
|
||||
case Hexagon::COMBINE_rr_cdnNotPt :
|
||||
case Hexagon::ASLH_cNotPt_V4 :
|
||||
case Hexagon::ASLH_cdnNotPt_V4 :
|
||||
case Hexagon::ASRH_cNotPt_V4 :
|
||||
case Hexagon::ASRH_cdnNotPt_V4 :
|
||||
case Hexagon::SXTB_cNotPt_V4 :
|
||||
case Hexagon::SXTB_cdnNotPt_V4 :
|
||||
case Hexagon::SXTH_cNotPt_V4 :
|
||||
case Hexagon::SXTH_cdnNotPt_V4 :
|
||||
case Hexagon::ZXTB_cNotPt_V4 :
|
||||
case Hexagon::ZXTB_cdnNotPt_V4 :
|
||||
case Hexagon::ZXTH_cNotPt_V4 :
|
||||
case Hexagon::ZXTH_cdnNotPt_V4 :
|
||||
|
||||
case Hexagon::LDd_GP_cNotPt_V4 :
|
||||
case Hexagon::LDb_GP_cNotPt_V4 :
|
||||
case Hexagon::LDub_GP_cNotPt_V4 :
|
||||
case Hexagon::LDh_GP_cNotPt_V4 :
|
||||
case Hexagon::LDuh_GP_cNotPt_V4 :
|
||||
case Hexagon::LDw_GP_cNotPt_V4 :
|
||||
case Hexagon::STd_GP_cNotPt_V4 :
|
||||
case Hexagon::STb_GP_cNotPt_V4 :
|
||||
case Hexagon::STh_GP_cNotPt_V4 :
|
||||
case Hexagon::STw_GP_cNotPt_V4 :
|
||||
case Hexagon::LDd_GP_cdnNotPt_V4 :
|
||||
case Hexagon::LDb_GP_cdnNotPt_V4 :
|
||||
case Hexagon::LDub_GP_cdnNotPt_V4 :
|
||||
case Hexagon::LDh_GP_cdnNotPt_V4 :
|
||||
case Hexagon::LDuh_GP_cdnNotPt_V4 :
|
||||
case Hexagon::LDw_GP_cdnNotPt_V4 :
|
||||
case Hexagon::STd_GP_cdnNotPt_V4 :
|
||||
case Hexagon::STb_GP_cdnNotPt_V4 :
|
||||
case Hexagon::STh_GP_cdnNotPt_V4 :
|
||||
case Hexagon::STw_GP_cdnNotPt_V4 :
|
||||
return false;
|
||||
}
|
||||
// return *some value* to avoid compiler warning
|
||||
return false;
|
||||
return PK_False;
|
||||
}
|
||||
|
||||
static MachineOperand& GetPostIncrementOperand(MachineInstr *MI,
|
||||
@ -1842,7 +1326,7 @@ bool HexagonPacketizerList::CanPromoteToNewValueStore( MachineInstr *MI,
|
||||
|
||||
if (( predRegNumDst != predRegNumSrc) ||
|
||||
QII->isDotNewInst(PacketMI) != QII->isDotNewInst(MI) ||
|
||||
GetPredicateSense(MI, QII) != GetPredicateSense(PacketMI, QII)) {
|
||||
getPredicateSense(MI, QII) != getPredicateSense(PacketMI, QII)) {
|
||||
return false;
|
||||
}
|
||||
}
|
||||
@ -1968,7 +1452,7 @@ bool HexagonPacketizerList::CanPromoteToDotNew( MachineInstr *MI,
|
||||
else {
|
||||
// Create a dot new machine instruction to see if resources can be
|
||||
// allocated. If not, bail out now.
|
||||
int NewOpcode = GetDotNewOp(MI->getOpcode());
|
||||
int NewOpcode = QII->GetDotNewOp(MI);
|
||||
const MCInstrDesc &desc = QII->get(NewOpcode);
|
||||
DebugLoc dl;
|
||||
MachineInstr *NewMI =
|
||||
@ -2109,7 +1593,7 @@ bool HexagonPacketizerList::ArePredicatesComplements (MachineInstr* MI1,
|
||||
// We also need to differentiate .old vs. .new:
|
||||
// !p0 is not complimentary to p0.new
|
||||
return ((MI1->getOperand(1).getReg() == MI2->getOperand(1).getReg()) &&
|
||||
(GetPredicateSense(MI1, QII) != GetPredicateSense(MI2, QII)) &&
|
||||
(getPredicateSense(MI1, QII) != getPredicateSense(MI2, QII)) &&
|
||||
(QII->isDotNewInst(MI1) == QII->isDotNewInst(MI2)));
|
||||
}
|
||||
|
||||
|
||||
28
test/CodeGen/Hexagon/pred-gp.ll
Normal file
28
test/CodeGen/Hexagon/pred-gp.ll
Normal file
@ -0,0 +1,28 @@
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
|
||||
; Check that we are able to predicate instructions with gp-relative
|
||||
; addressing mode.
|
||||
|
||||
@d = external global i32
|
||||
@c = common global i32 0, align 4
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define i32 @test2(i8 zeroext %a, i8 zeroext %b) #0 {
|
||||
; CHECK: if{{ *}}({{!*}}p{{[0-3]+}}{{[.new]*}}){{ *}}r{{[0-9]+}}{{ *}}={{ *}}memw(##{{[cd]}})
|
||||
; CHECK: if{{ *}}({{!*}}p{{[0-3]+}}){{ *}}r{{[0-9]+}}{{ *}}={{ *}}memw(##{{[cd]}})
|
||||
entry:
|
||||
%cmp = icmp eq i8 %a, %b
|
||||
br i1 %cmp, label %if.then, label %entry.if.end_crit_edge
|
||||
|
||||
entry.if.end_crit_edge:
|
||||
%.pre = load i32* @c, align 4
|
||||
br label %if.end
|
||||
|
||||
if.then:
|
||||
%0 = load i32* @d, align 4
|
||||
store i32 %0, i32* @c, align 4
|
||||
br label %if.end
|
||||
|
||||
if.end:
|
||||
%1 = phi i32 [ %.pre, %entry.if.end_crit_edge ], [ %0, %if.then ]
|
||||
ret i32 %1
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user