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https://github.com/RPCS3/llvm-mirror.git
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CellSPU:
Incorporate Tilmann's 128-bit operation patch. Evidently, it gets the llvm-gcc bootstrap a bit further along. llvm-svn: 67048
This commit is contained in:
Scott Michel
parent
f8afc9ecda
commit
2e2bccf754
@ -779,7 +779,7 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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result = DAG.getNode(SPUISD::SHUFB, dl, vecVT,
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vectorizeOp, alignLoadVec,
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DAG.getNode(ISD::BIT_CONVERT, dl,
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DAG.getNode(ISD::BIT_CONVERT, dl,
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MVT::v4i32, insertEltOp));
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result = DAG.getStore(the_chain, dl, result, basePtr,
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@ -1035,7 +1035,7 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
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ArgOffset += StackSlotSize;
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}
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if (!MemOps.empty())
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Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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&MemOps[0], MemOps.size());
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}
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@ -1156,7 +1156,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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// and flag operands which copy the outgoing args into the appropriate regs.
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SDValue InFlag;
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for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
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Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
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Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
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RegsToPass[i].second, InFlag);
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InFlag = Chain.getValue(1);
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}
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@ -1239,7 +1239,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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case MVT::Other: break;
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case MVT::i32:
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if (TheCall->getValueType(1) == MVT::i32) {
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Chain = DAG.getCopyFromReg(Chain, dl, SPU::R4,
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Chain = DAG.getCopyFromReg(Chain, dl, SPU::R4,
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MVT::i32, InFlag).getValue(1);
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ResultVals[0] = Chain.getValue(0);
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Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i32,
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@ -1247,20 +1247,20 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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ResultVals[1] = Chain.getValue(0);
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NumResults = 2;
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} else {
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Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i32,
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Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i32,
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InFlag).getValue(1);
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ResultVals[0] = Chain.getValue(0);
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NumResults = 1;
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}
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break;
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case MVT::i64:
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Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i64,
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Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i64,
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InFlag).getValue(1);
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ResultVals[0] = Chain.getValue(0);
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NumResults = 1;
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break;
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case MVT::i128:
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Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i128,
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Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i128,
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InFlag).getValue(1);
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ResultVals[0] = Chain.getValue(0);
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NumResults = 1;
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@ -1860,7 +1860,7 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
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DAG.getTargetConstant(V2Elt, MVT::i32),
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DAG.getCopyFromReg(InitTempReg, dl, VReg, PtrVT));
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// Use shuffle mask in SHUFB synthetic instruction:
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return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V2, V1,
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return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V2, V1,
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ShufMaskOp);
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} else if (rotate) {
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int rotamt = (MaxElts - V0Elt) * EltVT.getSizeInBits()/8;
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@ -2401,7 +2401,7 @@ static SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) {
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SDValue Comp1 =
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DAG.getNode(ISD::SRL, dl, MVT::i32,
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DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i32),
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DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i32),
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Shift1);
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SDValue Sum1 =
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@ -2588,7 +2588,7 @@ static SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG,
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}
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SDValue result =
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DAG.getSetCC(dl, ccResultVT, lhsSelect, rhsSelect,
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DAG.getSetCC(dl, ccResultVT, lhsSelect, rhsSelect,
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(ISD::CondCode) compareOp);
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if ((CC->get() & 0x8) == 0) {
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@ -2649,14 +2649,15 @@ static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
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//! Custom lower ISD::TRUNCATE
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static SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG)
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{
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// Type to truncate to
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MVT VT = Op.getValueType();
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MVT::SimpleValueType simpleVT = VT.getSimpleVT();
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MVT VecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits()));
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DebugLoc dl = Op.getDebugLoc();
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// Type to truncate from
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SDValue Op0 = Op.getOperand(0);
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MVT Op0VT = Op0.getValueType();
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MVT Op0VecVT = MVT::getVectorVT(Op0VT, (128 / Op0VT.getSizeInBits()));
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if (Op0VT.getSimpleVT() == MVT::i128 && simpleVT == MVT::i64) {
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// Create shuffle mask, least significant doubleword of quadword
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@ -2669,15 +2670,10 @@ static SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG)
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DAG.getConstant(maskHigh, MVT::i32),
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DAG.getConstant(maskLow, MVT::i32));
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SDValue truncShuffle = DAG.getNode(SPUISD::SHUFB, dl, VecVT,
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Op0, Op0, shufMask);
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SDValue PromoteScalar = DAG.getNode(SPUISD::PREFSLOT2VEC, dl,
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Op0VecVT, Op0);
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SDValue truncShuffle = DAG.getNode(SPUISD::SHUFB, dl, Op0VecVT,
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PromoteScalar, PromoteScalar, shufMask);
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return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT,
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DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, truncShuffle));
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return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, truncShuffle);
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}
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return SDValue(); // Leave the truncate unmolested
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@ -133,18 +133,22 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
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case SPU::ORi128_f32:
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case SPU::ORi128_r16:
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case SPU::ORi128_r8:
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*/
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case SPU::ORi128_vec:
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/*
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case SPU::ORr64_i128:
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case SPU::ORf64_i128:
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case SPU::ORr32_i128:
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case SPU::ORf32_i128:
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case SPU::ORr16_i128:
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case SPU::ORr8_i128:
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case SPU::ORvec_i128:
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*/
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case SPU::ORvec_i128:
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/*
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case SPU::ORr16_r32:
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case SPU::ORr8_r32:
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case SPU::ORf32_r32:
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case SPU::ORr32_f32:
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case SPU::ORr32_r16:
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case SPU::ORr32_r8:
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case SPU::ORr16_r64:
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@ -177,6 +181,7 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
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case SPU::ORr16:
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case SPU::ORr32:
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case SPU::ORr64:
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case SPU::ORr128:
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case SPU::ORf32:
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case SPU::ORf64:
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assert(MI.getNumOperands() == 3 &&
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@ -1429,9 +1429,6 @@ class ORExtractElt<RegisterClass rclass>:
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/* class ORCvtRegGPRC<RegisterClass rclass>:
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ORCvtForm<(outs GPRC:$rT), (ins rclass:$rA)>; */
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/* class ORCvtVecGPRC:
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ORCvtForm<(outs GPRC:$rT), (ins VECREG:$rA)>; */
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/* class ORCvtGPRCReg<RegisterClass rclass>:
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ORCvtForm<(outs rclass:$rT), (ins GPRC:$rA)>; */
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@ -1447,8 +1444,11 @@ class ORCvtFormR64Reg<RegisterClass rclass, list<dag> pattern = [ ]>:
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class ORCvtFormRegR64<RegisterClass rclass, list<dag> pattern = [ ]>:
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ORCvtForm<(outs R64C:$rT), (ins rclass:$rA), pattern>;
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/* class ORCvtGPRCVec:
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ORCvtForm<(outs VECREG:$rT), (ins GPRC:$rA)>; */
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class ORCvtGPRCVec:
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ORCvtForm<(outs VECREG:$rT), (ins GPRC:$rA)>;
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class ORCvtVecGPRC:
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ORCvtForm<(outs GPRC:$rT), (ins VECREG:$rA)>;
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multiclass BitwiseOr
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{
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@ -1496,8 +1496,14 @@ multiclass BitwiseOr
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def f32_v4f32: ORExtractElt<R32FP>;
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def f64_v2f64: ORExtractElt<R64FP>;
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// Conversion from vector to GPRC
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def i128_vec: ORCvtVecGPRC;
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// Conversion from GPRC to vector
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def vec_i128: ORCvtGPRCVec;
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/*
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// Conversion from GPRC to register
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// Conversion from register to GPRC
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def i128_r64: ORCvtRegGPRC<R64C>;
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def i128_f64: ORCvtRegGPRC<R64FP>;
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def i128_r32: ORCvtRegGPRC<R32C>;
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@ -1505,36 +1511,30 @@ multiclass BitwiseOr
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def i128_r16: ORCvtRegGPRC<R16C>;
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def i128_r8: ORCvtRegGPRC<R8C>;
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// Conversion from GPRC to vector
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def i128_vec: ORCvtVecGPRC;
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// Conversion from register to GPRC
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// Conversion from GPRC to register
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def r64_i128: ORCvtGPRCReg<R64C>;
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def f64_i128: ORCvtGPRCReg<R64FP>;
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def r32_i128: ORCvtGPRCReg<R32C>;
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def f32_i128: ORCvtGPRCReg<R32FP>;
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def r16_i128: ORCvtGPRCReg<R16C>;
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def r8_i128: ORCvtGPRCReg<R8C>;
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// Conversion from vector to GPRC
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def vec_i128: ORCvtGPRCVec;
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*/
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/*
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// Conversion from register to R32C:
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def r16_r32: ORCvtFormRegR32<R16C>;
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def r8_r32: ORCvtFormRegR32<R8C>;
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def r32_r16: ORCvtFormRegR32<R16C>;
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def r32_r8: ORCvtFormRegR32<R8C>;
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// Conversion from R32C to register
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def r32_r16: ORCvtFormR32Reg<R16C>;
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def r32_r8: ORCvtFormR32Reg<R8C>;
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*/
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// Conversion to register from R64C:
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// Conversion from R64C to register:
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def r32_r64: ORCvtFormR64Reg<R32C>;
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// def r16_r64: ORCvtFormR64Reg<R16C>;
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// def r8_r64: ORCvtFormR64Reg<R8C>;
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// Conversion to R64C from register
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// Conversion to R64C from register:
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def r64_r32: ORCvtFormRegR64<R32C>;
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// def r64_r16: ORCvtFormRegR64<R16C>;
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// def r64_r8: ORCvtFormRegR64<R8C>;
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@ -1659,6 +1659,7 @@ multiclass BitwiseOrComplement
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def v4i32: ORCVecInst<v4i32>;
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def v2i64: ORCVecInst<v2i64>;
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def r128: ORCRegInst<GPRC>;
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def r64: ORCRegInst<R64C>;
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def r32: ORCRegInst<R32C>;
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def r16: ORCRegInst<R16C>;
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@ -1840,72 +1841,64 @@ def XORIr32:
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[(set R32C:$rT, (xor R32C:$rA, i32ImmSExt10:$val))]>;
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// NAND:
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def NANDv16i8:
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RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"nand\t$rT, $rA, $rB", IntegerOp,
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[(set (v16i8 VECREG:$rT), (vnot (and (v16i8 VECREG:$rA),
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(v16i8 VECREG:$rB))))]>;
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def NANDv8i16:
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RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"nand\t$rT, $rA, $rB", IntegerOp,
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[(set (v8i16 VECREG:$rT), (vnot (and (v8i16 VECREG:$rA),
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(v8i16 VECREG:$rB))))]>;
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class NANDInst<dag OOL, dag IOL, list<dag> pattern>:
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RRForm<0b10010011000, OOL, IOL, "nand\t$rT, $rA, $rB",
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IntegerOp, pattern>;
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def NANDv4i32:
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RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"nand\t$rT, $rA, $rB", IntegerOp,
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[(set (v4i32 VECREG:$rT), (vnot (and (v4i32 VECREG:$rA),
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(v4i32 VECREG:$rB))))]>;
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class NANDVecInst<ValueType vectype>:
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NANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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[(set (vectype VECREG:$rT), (vnot (and (vectype VECREG:$rA),
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(vectype VECREG:$rB))))]>;
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class NANDRegInst<RegisterClass rclass>:
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NANDInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
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[(set rclass:$rT, (not (and rclass:$rA, rclass:$rB)))]>;
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def NANDr32:
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RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
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"nand\t$rT, $rA, $rB", IntegerOp,
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[(set R32C:$rT, (not (and R32C:$rA, R32C:$rB)))]>;
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multiclass BitwiseNand
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{
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def v16i8: NANDVecInst<v16i8>;
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def v8i16: NANDVecInst<v8i16>;
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def v4i32: NANDVecInst<v4i32>;
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def v2i64: NANDVecInst<v2i64>;
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def NANDr16:
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RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
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"nand\t$rT, $rA, $rB", IntegerOp,
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[(set R16C:$rT, (not (and R16C:$rA, R16C:$rB)))]>;
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def r128: NANDRegInst<GPRC>;
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def r64: NANDRegInst<R64C>;
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def r32: NANDRegInst<R32C>;
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def r16: NANDRegInst<R16C>;
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def r8: NANDRegInst<R8C>;
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}
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def NANDr8:
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RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
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"nand\t$rT, $rA, $rB", IntegerOp,
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[(set R8C:$rT, (not (and R8C:$rA, R8C:$rB)))]>;
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defm NAND : BitwiseNand;
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// NOR:
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def NORv16i8:
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RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"nor\t$rT, $rA, $rB", IntegerOp,
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[(set (v16i8 VECREG:$rT), (vnot (or (v16i8 VECREG:$rA),
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(v16i8 VECREG:$rB))))]>;
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def NORv8i16:
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RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"nor\t$rT, $rA, $rB", IntegerOp,
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[(set (v8i16 VECREG:$rT), (vnot (or (v8i16 VECREG:$rA),
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(v8i16 VECREG:$rB))))]>;
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class NORInst<dag OOL, dag IOL, list<dag> pattern>:
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RRForm<0b10010010000, OOL, IOL, "nor\t$rT, $rA, $rB",
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IntegerOp, pattern>;
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def NORv4i32:
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RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"nor\t$rT, $rA, $rB", IntegerOp,
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[(set (v4i32 VECREG:$rT), (vnot (or (v4i32 VECREG:$rA),
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(v4i32 VECREG:$rB))))]>;
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class NORVecInst<ValueType vectype>:
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NORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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[(set (vectype VECREG:$rT), (vnot (or (vectype VECREG:$rA),
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(vectype VECREG:$rB))))]>;
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class NORRegInst<RegisterClass rclass>:
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NORInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
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[(set rclass:$rT, (not (or rclass:$rA, rclass:$rB)))]>;
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def NORr32:
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RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
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"nor\t$rT, $rA, $rB", IntegerOp,
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[(set R32C:$rT, (not (or R32C:$rA, R32C:$rB)))]>;
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multiclass BitwiseNor
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{
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def v16i8: NORVecInst<v16i8>;
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def v8i16: NORVecInst<v8i16>;
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def v4i32: NORVecInst<v4i32>;
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def v2i64: NORVecInst<v2i64>;
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def NORr16:
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RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
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"nor\t$rT, $rA, $rB", IntegerOp,
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[(set R16C:$rT, (not (or R16C:$rA, R16C:$rB)))]>;
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def r128: NORRegInst<GPRC>;
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def r64: NORRegInst<R64C>;
|
||||
def r32: NORRegInst<R32C>;
|
||||
def r16: NORRegInst<R16C>;
|
||||
def r8: NORRegInst<R8C>;
|
||||
}
|
||||
|
||||
def NORr8:
|
||||
RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
|
||||
"nor\t$rT, $rA, $rB", IntegerOp,
|
||||
[(set R8C:$rT, (not (or R8C:$rA, R8C:$rB)))]>;
|
||||
defm NOR : BitwiseNor;
|
||||
|
||||
// Select bits:
|
||||
class SELBInst<dag OOL, dag IOL, list<dag> pattern>:
|
||||
@ -4361,8 +4354,7 @@ def LNOP : SPUInstr<(outs), (ins), "lnop", LoadNOP> {
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Bit conversions (type conversions between vector/packed types)
|
||||
// NOTE: Promotions are handled using the XS* instructions. Truncation
|
||||
// is not handled.
|
||||
// NOTE: Promotions are handled using the XS* instructions.
|
||||
//===----------------------------------------------------------------------===//
|
||||
def : Pat<(v16i8 (bitconvert (v8i16 VECREG:$src))), (v16i8 VECREG:$src)>;
|
||||
def : Pat<(v16i8 (bitconvert (v4i32 VECREG:$src))), (v16i8 VECREG:$src)>;
|
||||
@ -4400,8 +4392,31 @@ def : Pat<(v2f64 (bitconvert (v4i32 VECREG:$src))), (v2f64 VECREG:$src)>;
|
||||
def : Pat<(v2f64 (bitconvert (v2i64 VECREG:$src))), (v2f64 VECREG:$src)>;
|
||||
def : Pat<(v2f64 (bitconvert (v2f64 VECREG:$src))), (v2f64 VECREG:$src)>;
|
||||
|
||||
def : Pat<(f32 (bitconvert (i32 R32C:$src))), (f32 R32FP:$src)>;
|
||||
def : Pat<(f64 (bitconvert (i64 R64C:$src))), (f64 R64FP:$src)>;
|
||||
def : Pat<(i128 (bitconvert (v16i8 VECREG:$src))),
|
||||
(ORi128_vec VECREG:$src)>;
|
||||
def : Pat<(i128 (bitconvert (v8i16 VECREG:$src))),
|
||||
(ORi128_vec VECREG:$src)>;
|
||||
def : Pat<(i128 (bitconvert (v4i32 VECREG:$src))),
|
||||
(ORi128_vec VECREG:$src)>;
|
||||
def : Pat<(i128 (bitconvert (v2i64 VECREG:$src))),
|
||||
(ORi128_vec VECREG:$src)>;
|
||||
def : Pat<(i128 (bitconvert (v4f32 VECREG:$src))),
|
||||
(ORi128_vec VECREG:$src)>;
|
||||
def : Pat<(i128 (bitconvert (v2f64 VECREG:$src))),
|
||||
(ORi128_vec VECREG:$src)>;
|
||||
|
||||
def : Pat<(v16i8 (bitconvert (i128 GPRC:$src))),
|
||||
(v16i8 (ORvec_i128 GPRC:$src))>;
|
||||
def : Pat<(v8i16 (bitconvert (i128 GPRC:$src))),
|
||||
(v8i16 (ORvec_i128 GPRC:$src))>;
|
||||
def : Pat<(v4i32 (bitconvert (i128 GPRC:$src))),
|
||||
(v4i32 (ORvec_i128 GPRC:$src))>;
|
||||
def : Pat<(v2i64 (bitconvert (i128 GPRC:$src))),
|
||||
(v2i64 (ORvec_i128 GPRC:$src))>;
|
||||
def : Pat<(v4f32 (bitconvert (i128 GPRC:$src))),
|
||||
(v4f32 (ORvec_i128 GPRC:$src))>;
|
||||
def : Pat<(v2f64 (bitconvert (i128 GPRC:$src))),
|
||||
(v2f64 (ORvec_i128 GPRC:$src))>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Instruction patterns:
|
||||
@ -4598,7 +4613,7 @@ def : Pat<(add (SPUhi tjumptable:$in, 0), (SPUlo tjumptable:$in, 0)),
|
||||
def : Pat<(add (SPUhi tconstpool:$in, 0), (SPUlo tconstpool:$in, 0)),
|
||||
(IOHLlo (ILHUhi tconstpool:$in), tconstpool:$in)>;
|
||||
|
||||
// Instrinsics:
|
||||
// Intrinsics:
|
||||
include "CellSDKIntrinsics.td"
|
||||
// Various math operator instruction sequences
|
||||
include "SPUMathInstr.td"
|
||||
|
||||
@ -1,76 +1,94 @@
|
||||
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
|
||||
; RUN: grep shufb %t1.s | count 10
|
||||
; RUN: grep shufb %t1.s | count 19
|
||||
; RUN: grep {ilhu.*1799} %t1.s | count 1
|
||||
; RUN: grep {ilhu.*771} %t1.s | count 1
|
||||
; RUN: grep {ilhu.*771} %t1.s | count 2
|
||||
; RUN: grep {ilhu.*1543} %t1.s | count 1
|
||||
; RUN: grep {ilhu.*1029} %t1.s | count 1
|
||||
; RUN: grep {ilhu.*515} %t1.s | count 2
|
||||
; RUN: grep xsbh %t1.s | count 2
|
||||
; RUN: grep sfh %t1.s | count 1
|
||||
; RUN: grep {ilhu.*515} %t1.s | count 1
|
||||
; RUN: grep {ilhu.*3855} %t1.s | count 1
|
||||
; RUN: grep {ilhu.*3599} %t1.s | count 1
|
||||
; RUN: grep {ilhu.*3085} %t1.s | count 1
|
||||
; RUN: grep {iohl.*3855} %t1.s | count 1
|
||||
; RUN: grep {iohl.*3599} %t1.s | count 2
|
||||
; RUN: grep {iohl.*1543} %t1.s | count 2
|
||||
; RUN: grep {iohl.*771} %t1.s | count 2
|
||||
; RUN: grep {iohl.*515} %t1.s | count 1
|
||||
; RUN: grep {iohl.*1799} %t1.s | count 1
|
||||
; RUN: grep lqa %t1.s | count 1
|
||||
; RUN: grep cbd %t1.s | count 4
|
||||
; RUN: grep chd %t1.s | count 3
|
||||
; RUN: grep cwd %t1.s | count 1
|
||||
; RUN: grep cdd %t1.s | count 1
|
||||
|
||||
; ModuleID = 'trunc.bc'
|
||||
target datalayout = "E-p:32:32:128-i1:8:128-i8:8:128-i16:16:128-i32:32:128-i64:32:128-f32:32:128-f64:64:128-v64:64:64-v128:128:128-a0:0:128-s0:128:128"
|
||||
target triple = "spu"
|
||||
|
||||
; codegen for i128 arguments is not implemented yet on CellSPU
|
||||
; once this changes uncomment the functions below
|
||||
; and update the expected results accordingly
|
||||
|
||||
;define i8 @trunc_i128_i8(i128 %u) nounwind readnone {
|
||||
;entry:
|
||||
; %0 = trunc i128 %u to i8
|
||||
; ret i8 %0
|
||||
;}
|
||||
;define i16 @trunc_i128_i16(i128 %u) nounwind readnone {
|
||||
;entry:
|
||||
; %0 = trunc i128 %u to i16
|
||||
; ret i16 %0
|
||||
;}
|
||||
;define i32 @trunc_i128_i32(i128 %u) nounwind readnone {
|
||||
;entry:
|
||||
; %0 = trunc i128 %u to i32
|
||||
; ret i32 %0
|
||||
;}
|
||||
;define i64 @trunc_i128_i64(i128 %u) nounwind readnone {
|
||||
;entry:
|
||||
; %0 = trunc i128 %u to i64
|
||||
; ret i64 %0
|
||||
;}
|
||||
|
||||
define <16 x i8> @trunc_i64_i8(i64 %u, <16 x i8> %v) nounwind readnone {
|
||||
define <16 x i8> @trunc_i128_i8(i128 %u, <16 x i8> %v) {
|
||||
entry:
|
||||
%0 = trunc i64 %u to i8
|
||||
%tmp1 = insertelement <16 x i8> %v, i8 %0, i32 10
|
||||
ret <16 x i8> %tmp1
|
||||
}
|
||||
define <8 x i16> @trunc_i64_i16(i64 %u, <8 x i16> %v) nounwind readnone {
|
||||
entry:
|
||||
%0 = trunc i64 %u to i16
|
||||
%tmp1 = insertelement <8 x i16> %v, i16 %0, i32 6
|
||||
ret <8 x i16> %tmp1
|
||||
}
|
||||
define i32 @trunc_i64_i32(i64 %u, i32 %v) nounwind readnone {
|
||||
entry:
|
||||
%0 = trunc i64 %u to i32
|
||||
ret i32 %0
|
||||
%0 = trunc i128 %u to i8
|
||||
%tmp1 = insertelement <16 x i8> %v, i8 %0, i32 15
|
||||
ret <16 x i8> %tmp1
|
||||
}
|
||||
|
||||
define i8 @trunc_i32_i8(i32 %u, i8 %v) nounwind readnone {
|
||||
define <8 x i16> @trunc_i128_i16(i128 %u, <8 x i16> %v) {
|
||||
entry:
|
||||
%0 = trunc i32 %u to i8
|
||||
%1 = sub i8 %0, %v
|
||||
ret i8 %1
|
||||
}
|
||||
define <8 x i16> @trunc_i32_i16(i32 %u, <8 x i16> %v) nounwind readnone {
|
||||
entry:
|
||||
%0 = trunc i32 %u to i16
|
||||
%tmp1 = insertelement <8 x i16> %v, i16 %0, i32 3
|
||||
ret <8 x i16> %tmp1
|
||||
%0 = trunc i128 %u to i16
|
||||
%tmp1 = insertelement <8 x i16> %v, i16 %0, i32 8
|
||||
ret <8 x i16> %tmp1
|
||||
}
|
||||
|
||||
define <16 x i8> @trunc_i16_i8(i16 %u, <16 x i8> %v) nounwind readnone {
|
||||
define <4 x i32> @trunc_i128_i32(i128 %u, <4 x i32> %v) {
|
||||
entry:
|
||||
%0 = trunc i16 %u to i8
|
||||
%tmp1 = insertelement <16 x i8> %v, i8 %0, i32 5
|
||||
ret <16 x i8> %tmp1
|
||||
%0 = trunc i128 %u to i32
|
||||
%tmp1 = insertelement <4 x i32> %v, i32 %0, i32 2
|
||||
ret <4 x i32> %tmp1
|
||||
}
|
||||
|
||||
define <2 x i64> @trunc_i128_i64(i128 %u, <2 x i64> %v) {
|
||||
entry:
|
||||
%0 = trunc i128 %u to i64
|
||||
%tmp1 = insertelement <2 x i64> %v, i64 %0, i32 1
|
||||
ret <2 x i64> %tmp1
|
||||
}
|
||||
|
||||
define <16 x i8> @trunc_i64_i8(i64 %u, <16 x i8> %v) {
|
||||
entry:
|
||||
%0 = trunc i64 %u to i8
|
||||
%tmp1 = insertelement <16 x i8> %v, i8 %0, i32 10
|
||||
ret <16 x i8> %tmp1
|
||||
}
|
||||
|
||||
define <8 x i16> @trunc_i64_i16(i64 %u, <8 x i16> %v) {
|
||||
entry:
|
||||
%0 = trunc i64 %u to i16
|
||||
%tmp1 = insertelement <8 x i16> %v, i16 %0, i32 6
|
||||
ret <8 x i16> %tmp1
|
||||
}
|
||||
|
||||
define i32 @trunc_i64_i32(i64 %u) {
|
||||
entry:
|
||||
%0 = trunc i64 %u to i32
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define <16 x i8> @trunc_i32_i8(i32 %u, <16 x i8> %v) {
|
||||
entry:
|
||||
%0 = trunc i32 %u to i8
|
||||
%tmp1 = insertelement <16 x i8> %v, i8 %0, i32 7
|
||||
ret <16 x i8> %tmp1
|
||||
}
|
||||
|
||||
define <8 x i16> @trunc_i32_i16(i32 %u, <8 x i16> %v) {
|
||||
entry:
|
||||
%0 = trunc i32 %u to i16
|
||||
%tmp1 = insertelement <8 x i16> %v, i16 %0, i32 3
|
||||
ret <8 x i16> %tmp1
|
||||
}
|
||||
|
||||
define <16 x i8> @trunc_i16_i8(i16 %u, <16 x i8> %v) {
|
||||
entry:
|
||||
%0 = trunc i16 %u to i8
|
||||
%tmp1 = insertelement <16 x i8> %v, i8 %0, i32 5
|
||||
ret <16 x i8> %tmp1
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user