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[DAGCombiner] use narrow vector ops to eliminate concat/extract (PR32790)
In the best case:
extract (binop (concat X1, X2), (concat Y1, Y2)), N --> binop XN, YN
...we kill all of the extract/concat and just have narrow binops remaining.
If only one of the binop operands is amenable, this transform is still
worthwhile because we kill some of the extract/concat.
Optional bitcasting makes the code more complicated, but there doesn't
seem to be a way to avoid that.
The TODO about extending to more than bitwise logic is there because we really
will regress several x86 tests including madd, psad, and even a plain
integer-multiply-by-2 or shift-left-by-1. I don't think there's anything
fundamentally wrong with this patch that would cause those regressions; those
folds are just missing or brittle.
If we extend to more binops, I found that this patch will fire on at least one
non-x86 regression test. There's an ARM NEON test in
test/CodeGen/ARM/coalesce-subregs.ll with a pattern like:
t5: v2f32 = vector_shuffle<0,3> t2, t4
t6: v1i64 = bitcast t5
t8: v1i64 = BUILD_VECTOR Constant:i64<0>
t9: v2i64 = concat_vectors t6, t8
t10: v4f32 = bitcast t9
t12: v4f32 = fmul t11, t10
t13: v2i64 = bitcast t12
t16: v1i64 = extract_subvector t13, Constant:i32<0>
There was no functional change in the codegen from this transform from what I
could see though.
For the x86 test changes:
1. PR32790() is the closest call. We don't reduce the AVX1 instruction count in that case,
but we improve throughput. Also, on a core like Jaguar that double-pumps 256-bit ops,
there's an unseen win because two 128-bit ops have the same cost as the wider 256-bit op.
SSE/AVX2/AXV512 are not affected which is expected because only AVX1 has the extract/concat
ops to match the pattern.
2. do_not_use_256bit_op() is the best case. Everyone wins by avoiding the concat/extract.
Related bug for IR filed as: https://bugs.llvm.org/show_bug.cgi?id=33026
3. The SSE diffs in vector-trunc-math.ll are just scheduling/RA, so nothing real AFAICT.
4. The AVX1 diffs in vector-tzcnt-256.ll are all the same pattern: we reduced the instruction
count by one in each case by eliminating two insert/extract while adding one narrower logic op.
https://bugs.llvm.org/show_bug.cgi?id=32790
Differential Revision: https://reviews.llvm.org/D33137
llvm-svn: 303997
This commit is contained in:
Sanjay Patel
parent
f2ddd9dff5
commit
2f7e4f8001
@ -14462,6 +14462,99 @@ SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
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return SDValue();
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}
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/// If we are extracting a subvector produced by a wide binary operator with at
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/// at least one operand that was the result of a vector concatenation, then try
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/// to use the narrow vector operands directly to avoid the concatenation and
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/// extraction.
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static SDValue narrowExtractedVectorBinOp(SDNode *Extract, SelectionDAG &DAG) {
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// TODO: Refactor with the caller (visitEXTRACT_SUBVECTOR), so we can share
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// some of these bailouts with other transforms.
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// The extract index must be a constant, so we can map it to a concat operand.
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auto *ExtractIndex = dyn_cast<ConstantSDNode>(Extract->getOperand(1));
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if (!ExtractIndex)
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return SDValue();
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// Only handle the case where we are doubling and then halving. A larger ratio
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// may require more than two narrow binops to replace the wide binop.
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EVT VT = Extract->getValueType(0);
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unsigned NumElems = VT.getVectorNumElements();
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assert((ExtractIndex->getZExtValue() % NumElems) == 0 &&
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"Extract index is not a multiple of the vector length.");
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if (Extract->getOperand(0).getValueSizeInBits() != VT.getSizeInBits() * 2)
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return SDValue();
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// We are looking for an optionally bitcasted wide vector binary operator
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// feeding an extract subvector.
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SDValue BinOp = Extract->getOperand(0);
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if (BinOp.getOpcode() == ISD::BITCAST)
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BinOp = BinOp.getOperand(0);
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// TODO: The motivating case for this transform is an x86 AVX1 target. That
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// target has temptingly almost legal versions of bitwise logic ops in 256-bit
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// flavors, but no other 256-bit integer support. This could be extended to
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// handle any binop, but that may require fixing/adding other folds to avoid
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// codegen regressions.
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unsigned BOpcode = BinOp.getOpcode();
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if (BOpcode != ISD::AND && BOpcode != ISD::OR && BOpcode != ISD::XOR)
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return SDValue();
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// The binop must be a vector type, so we can chop it in half.
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EVT WideBVT = BinOp.getValueType();
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if (!WideBVT.isVector())
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return SDValue();
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// Bail out if the target does not support a narrower version of the binop.
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EVT NarrowBVT = EVT::getVectorVT(*DAG.getContext(), WideBVT.getScalarType(),
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WideBVT.getVectorNumElements() / 2);
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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if (!TLI.isOperationLegalOrCustomOrPromote(BOpcode, NarrowBVT))
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return SDValue();
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// Peek through bitcasts of the binary operator operands if needed.
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SDValue LHS = BinOp.getOperand(0);
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if (LHS.getOpcode() == ISD::BITCAST)
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LHS = LHS.getOperand(0);
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SDValue RHS = BinOp.getOperand(1);
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if (RHS.getOpcode() == ISD::BITCAST)
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RHS = RHS.getOperand(0);
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// We need at least one concatenation operation of a binop operand to make
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// this transform worthwhile. The concat must double the input vector sizes.
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// TODO: Should we also handle INSERT_SUBVECTOR patterns?
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bool ConcatL =
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LHS.getOpcode() == ISD::CONCAT_VECTORS && LHS.getNumOperands() == 2;
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bool ConcatR =
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RHS.getOpcode() == ISD::CONCAT_VECTORS && RHS.getNumOperands() == 2;
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if (!ConcatL && !ConcatR)
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return SDValue();
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// If one of the binop operands was not the result of a concat, we must
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// extract a half-sized operand for our new narrow binop. We can't just reuse
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// the original extract index operand because we may have bitcasted.
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unsigned ConcatOpNum = ExtractIndex->getZExtValue() / NumElems;
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unsigned ExtBOIdx = ConcatOpNum * NarrowBVT.getVectorNumElements();
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EVT ExtBOIdxVT = Extract->getOperand(1).getValueType();
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SDLoc DL(Extract);
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// extract (binop (concat X1, X2), (concat Y1, Y2)), N --> binop XN, YN
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// extract (binop (concat X1, X2), Y), N --> binop XN, (extract Y, N)
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// extract (binop X, (concat Y1, Y2)), N --> binop (extract X, N), YN
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SDValue X = ConcatL ? DAG.getBitcast(NarrowBVT, LHS.getOperand(ConcatOpNum))
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: DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NarrowBVT,
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BinOp.getOperand(0),
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DAG.getConstant(ExtBOIdx, DL, ExtBOIdxVT));
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SDValue Y = ConcatR ? DAG.getBitcast(NarrowBVT, RHS.getOperand(ConcatOpNum))
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: DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NarrowBVT,
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BinOp.getOperand(1),
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DAG.getConstant(ExtBOIdx, DL, ExtBOIdxVT));
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SDValue NarrowBinOp = DAG.getNode(BOpcode, DL, NarrowBVT, X, Y);
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return DAG.getBitcast(VT, NarrowBinOp);
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}
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SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
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EVT NVT = N->getValueType(0);
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SDValue V = N->getOperand(0);
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@ -14517,6 +14610,9 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
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}
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}
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if (SDValue NarrowBOp = narrowExtractedVectorBinOp(N, DAG))
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return NarrowBOp;
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return SDValue();
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}
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@ -22,17 +22,17 @@ define <8 x i32> @PR32790(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i32> %d
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;
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; AVX1-LABEL: PR32790:
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm5
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; AVX1-NEXT: vpaddd %xmm4, %xmm5, %xmm4
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; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm4
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
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; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
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; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm0
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm2
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; AVX1-NEXT: vpsubd %xmm2, %xmm1, %xmm1
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; AVX1-NEXT: vpsubd %xmm3, %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm1
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; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm1
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; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vpand %xmm2, %xmm4, %xmm1
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; AVX1-NEXT: vpsubd %xmm3, %xmm1, %xmm1
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: PR32790:
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@ -60,46 +60,17 @@ define <8 x i32> @PR32790(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i32> %d
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define <4 x i32> @do_not_use_256bit_op(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
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; SSE-LABEL: do_not_use_256bit_op:
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; SSE: # BB#0:
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; SSE-NEXT: pand %xmm3, %xmm1
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; SSE-NEXT: pand %xmm2, %xmm0
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; SSE-NEXT: pand %xmm3, %xmm1
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; SSE-NEXT: psubd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: do_not_use_256bit_op:
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; AVX1: # BB#0:
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; AVX1-NEXT: # kill: %XMM2<def> %XMM2<kill> %YMM2<def>
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; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm1
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; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vzeroupper
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: do_not_use_256bit_op:
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; AVX2: # BB#0:
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; AVX2-NEXT: # kill: %XMM2<def> %XMM2<kill> %YMM2<def>
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; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
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; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
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; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm1
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; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVX2-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: vzeroupper
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: do_not_use_256bit_op:
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; AVX512: # BB#0:
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; AVX512-NEXT: # kill: %XMM2<def> %XMM2<kill> %YMM2<def>
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; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
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; AVX512-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
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; AVX512-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm1
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; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0
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; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVX512-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX512-NEXT: vzeroupper
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; AVX512-NEXT: retq
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; AVX-LABEL: do_not_use_256bit_op:
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; AVX: # BB#0:
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; AVX-NEXT: vpand %xmm2, %xmm0, %xmm0
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; AVX-NEXT: vpand %xmm3, %xmm1, %xmm1
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; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%concat1 = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%concat2 = shufflevector <4 x i32> %c, <4 x i32> %d, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%and = and <8 x i32> %concat1, %concat2
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@ -3030,10 +3030,10 @@ define <8 x i16> @trunc_and_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind {
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define <8 x i16> @trunc_and_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind {
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; SSE-LABEL: trunc_and_v8i32_v8i16:
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; SSE: # BB#0:
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; SSE-NEXT: pand %xmm2, %xmm0
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; SSE-NEXT: pand %xmm3, %xmm1
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; SSE-NEXT: pslld $16, %xmm1
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; SSE-NEXT: psrad $16, %xmm1
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; SSE-NEXT: pand %xmm2, %xmm0
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; SSE-NEXT: pslld $16, %xmm0
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; SSE-NEXT: psrad $16, %xmm0
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; SSE-NEXT: packssdw %xmm1, %xmm0
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@ -3786,10 +3786,10 @@ define <8 x i16> @trunc_xor_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind {
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define <8 x i16> @trunc_xor_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind {
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; SSE-LABEL: trunc_xor_v8i32_v8i16:
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; SSE: # BB#0:
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; SSE-NEXT: pxor %xmm2, %xmm0
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; SSE-NEXT: pxor %xmm3, %xmm1
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; SSE-NEXT: pslld $16, %xmm1
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; SSE-NEXT: psrad $16, %xmm1
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; SSE-NEXT: pxor %xmm2, %xmm0
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; SSE-NEXT: pslld $16, %xmm0
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; SSE-NEXT: psrad $16, %xmm0
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; SSE-NEXT: packssdw %xmm1, %xmm0
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@ -4542,10 +4542,10 @@ define <8 x i16> @trunc_or_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind {
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define <8 x i16> @trunc_or_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind {
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; SSE-LABEL: trunc_or_v8i32_v8i16:
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; SSE: # BB#0:
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; SSE-NEXT: por %xmm2, %xmm0
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; SSE-NEXT: por %xmm3, %xmm1
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; SSE-NEXT: pslld $16, %xmm1
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; SSE-NEXT: psrad $16, %xmm1
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; SSE-NEXT: por %xmm2, %xmm0
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; SSE-NEXT: pslld $16, %xmm0
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; SSE-NEXT: psrad $16, %xmm0
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; SSE-NEXT: packssdw %xmm1, %xmm0
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@ -13,11 +13,8 @@ define <4 x i64> @testv4i64(<4 x i64> %in) nounwind {
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX1-NEXT: vpsubq %xmm1, %xmm2, %xmm1
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; AVX1-NEXT: vpsubq %xmm0, %xmm2, %xmm3
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1
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; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vpsubq %xmm1, %xmm2, %xmm3
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; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
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; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1,1]
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; AVX1-NEXT: vpsubq %xmm3, %xmm1, %xmm1
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; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
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@ -29,6 +26,8 @@ define <4 x i64> @testv4i64(<4 x i64> %in) nounwind {
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; AVX1-NEXT: vpshufb %xmm1, %xmm6, %xmm1
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; AVX1-NEXT: vpaddb %xmm5, %xmm1, %xmm1
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; AVX1-NEXT: vpsadbw %xmm2, %xmm1, %xmm1
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; AVX1-NEXT: vpsubq %xmm0, %xmm2, %xmm5
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; AVX1-NEXT: vpand %xmm5, %xmm0, %xmm0
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; AVX1-NEXT: vpsubq %xmm3, %xmm0, %xmm0
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; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm3
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; AVX1-NEXT: vpshufb %xmm3, %xmm6, %xmm3
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@ -129,11 +128,8 @@ define <4 x i64> @testv4i64u(<4 x i64> %in) nounwind {
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX1-NEXT: vpsubq %xmm1, %xmm2, %xmm1
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; AVX1-NEXT: vpsubq %xmm0, %xmm2, %xmm3
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1
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; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vpsubq %xmm1, %xmm2, %xmm3
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; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
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; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1,1]
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; AVX1-NEXT: vpsubq %xmm3, %xmm1, %xmm1
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; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
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@ -145,6 +141,8 @@ define <4 x i64> @testv4i64u(<4 x i64> %in) nounwind {
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; AVX1-NEXT: vpshufb %xmm1, %xmm6, %xmm1
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; AVX1-NEXT: vpaddb %xmm5, %xmm1, %xmm1
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; AVX1-NEXT: vpsadbw %xmm2, %xmm1, %xmm1
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; AVX1-NEXT: vpsubq %xmm0, %xmm2, %xmm5
|
||||
; AVX1-NEXT: vpand %xmm5, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpsubq %xmm3, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm3
|
||||
; AVX1-NEXT: vpshufb %xmm3, %xmm6, %xmm3
|
||||
@ -228,28 +226,27 @@ define <4 x i64> @testv4i64u(<4 x i64> %in) nounwind {
|
||||
define <8 x i32> @testv8i32(<8 x i32> %in) nounwind {
|
||||
; AVX1-LABEL: testv8i32:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpsubd %xmm2, %xmm1, %xmm2
|
||||
; AVX1-NEXT: vpsubd %xmm0, %xmm1, %xmm3
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
|
||||
; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm0
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
|
||||
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpsubd %xmm1, %xmm2, %xmm3
|
||||
; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1,1,1,1]
|
||||
; AVX1-NEXT: vpsubd %xmm3, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpsubd %xmm3, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm2, %xmm5
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm1, %xmm5
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
|
||||
; AVX1-NEXT: vpshufb %xmm5, %xmm6, %xmm5
|
||||
; AVX1-NEXT: vpsrlw $4, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpshufb %xmm2, %xmm6, %xmm2
|
||||
; AVX1-NEXT: vpaddb %xmm5, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm5 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
|
||||
; AVX1-NEXT: vpsadbw %xmm1, %xmm5, %xmm5
|
||||
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm2 = xmm2[0],zero,xmm2[1],zero
|
||||
; AVX1-NEXT: vpsadbw %xmm1, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpackuswb %xmm5, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpshufb %xmm1, %xmm6, %xmm1
|
||||
; AVX1-NEXT: vpaddb %xmm5, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm5 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]
|
||||
; AVX1-NEXT: vpsadbw %xmm2, %xmm5, %xmm5
|
||||
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
|
||||
; AVX1-NEXT: vpsadbw %xmm2, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpackuswb %xmm5, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpsubd %xmm0, %xmm2, %xmm5
|
||||
; AVX1-NEXT: vpand %xmm5, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpsubd %xmm3, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm3
|
||||
; AVX1-NEXT: vpshufb %xmm3, %xmm6, %xmm3
|
||||
@ -257,12 +254,12 @@ define <8 x i32> @testv8i32(<8 x i32> %in) nounwind {
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm6, %xmm0
|
||||
; AVX1-NEXT: vpaddb %xmm3, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm3 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
|
||||
; AVX1-NEXT: vpsadbw %xmm1, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm3 = xmm0[2],xmm2[2],xmm0[3],xmm2[3]
|
||||
; AVX1-NEXT: vpsadbw %xmm2, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
|
||||
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpsadbw %xmm2, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpackuswb %xmm3, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: testv8i32:
|
||||
@ -369,28 +366,27 @@ define <8 x i32> @testv8i32(<8 x i32> %in) nounwind {
|
||||
define <8 x i32> @testv8i32u(<8 x i32> %in) nounwind {
|
||||
; AVX1-LABEL: testv8i32u:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpsubd %xmm2, %xmm1, %xmm2
|
||||
; AVX1-NEXT: vpsubd %xmm0, %xmm1, %xmm3
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
|
||||
; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm0
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
|
||||
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpsubd %xmm1, %xmm2, %xmm3
|
||||
; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1,1,1,1]
|
||||
; AVX1-NEXT: vpsubd %xmm3, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpsubd %xmm3, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm2, %xmm5
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm1, %xmm5
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
|
||||
; AVX1-NEXT: vpshufb %xmm5, %xmm6, %xmm5
|
||||
; AVX1-NEXT: vpsrlw $4, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpshufb %xmm2, %xmm6, %xmm2
|
||||
; AVX1-NEXT: vpaddb %xmm5, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm5 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
|
||||
; AVX1-NEXT: vpsadbw %xmm1, %xmm5, %xmm5
|
||||
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm2 = xmm2[0],zero,xmm2[1],zero
|
||||
; AVX1-NEXT: vpsadbw %xmm1, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpackuswb %xmm5, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpshufb %xmm1, %xmm6, %xmm1
|
||||
; AVX1-NEXT: vpaddb %xmm5, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm5 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]
|
||||
; AVX1-NEXT: vpsadbw %xmm2, %xmm5, %xmm5
|
||||
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
|
||||
; AVX1-NEXT: vpsadbw %xmm2, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpackuswb %xmm5, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpsubd %xmm0, %xmm2, %xmm5
|
||||
; AVX1-NEXT: vpand %xmm5, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpsubd %xmm3, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm3
|
||||
; AVX1-NEXT: vpshufb %xmm3, %xmm6, %xmm3
|
||||
@ -398,12 +394,12 @@ define <8 x i32> @testv8i32u(<8 x i32> %in) nounwind {
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm6, %xmm0
|
||||
; AVX1-NEXT: vpaddb %xmm3, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm3 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
|
||||
; AVX1-NEXT: vpsadbw %xmm1, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm3 = xmm0[2],xmm2[2],xmm0[3],xmm2[3]
|
||||
; AVX1-NEXT: vpsadbw %xmm2, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
|
||||
; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpsadbw %xmm2, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpackuswb %xmm3, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: testv8i32u:
|
||||
@ -487,32 +483,31 @@ define <8 x i32> @testv8i32u(<8 x i32> %in) nounwind {
|
||||
define <16 x i16> @testv16i16(<16 x i16> %in) nounwind {
|
||||
; AVX1-LABEL: testv16i16:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
|
||||
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpsubw %xmm1, %xmm2, %xmm1
|
||||
; AVX1-NEXT: vpsubw %xmm0, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
|
||||
; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,1,1,1,1,1,1,1]
|
||||
; AVX1-NEXT: vpsubw %xmm1, %xmm0, %xmm2
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
|
||||
; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm4
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
|
||||
; AVX1-NEXT: vpshufb %xmm4, %xmm5, %xmm4
|
||||
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpsubw %xmm0, %xmm1, %xmm2
|
||||
; AVX1-NEXT: vpand %xmm2, %xmm0, %xmm2
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1,1,1,1,1,1,1,1]
|
||||
; AVX1-NEXT: vpsubw %xmm3, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm2, %xmm5
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
|
||||
; AVX1-NEXT: vpshufb %xmm5, %xmm6, %xmm5
|
||||
; AVX1-NEXT: vpsrlw $4, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpshufb %xmm2, %xmm5, %xmm2
|
||||
; AVX1-NEXT: vpaddb %xmm4, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpsllw $8, %xmm2, %xmm4
|
||||
; AVX1-NEXT: vpaddb %xmm2, %xmm4, %xmm2
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpshufb %xmm2, %xmm6, %xmm2
|
||||
; AVX1-NEXT: vpaddb %xmm5, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpsllw $8, %xmm2, %xmm5
|
||||
; AVX1-NEXT: vpaddb %xmm2, %xmm5, %xmm2
|
||||
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
|
||||
; AVX1-NEXT: vpsubw %xmm1, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm1
|
||||
; AVX1-NEXT: vpshufb %xmm1, %xmm5, %xmm1
|
||||
; AVX1-NEXT: vpsubw %xmm0, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpsubw %xmm3, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm1
|
||||
; AVX1-NEXT: vpshufb %xmm1, %xmm6, %xmm1
|
||||
; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm5, %xmm0
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm6, %xmm0
|
||||
; AVX1-NEXT: vpaddb %xmm1, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpsllw $8, %xmm0, %xmm1
|
||||
; AVX1-NEXT: vpaddb %xmm0, %xmm1, %xmm0
|
||||
@ -621,32 +616,31 @@ define <16 x i16> @testv16i16(<16 x i16> %in) nounwind {
|
||||
define <16 x i16> @testv16i16u(<16 x i16> %in) nounwind {
|
||||
; AVX1-LABEL: testv16i16u:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
|
||||
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpsubw %xmm1, %xmm2, %xmm1
|
||||
; AVX1-NEXT: vpsubw %xmm0, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
|
||||
; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,1,1,1,1,1,1,1]
|
||||
; AVX1-NEXT: vpsubw %xmm1, %xmm0, %xmm2
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
|
||||
; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm4
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
|
||||
; AVX1-NEXT: vpshufb %xmm4, %xmm5, %xmm4
|
||||
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpsubw %xmm0, %xmm1, %xmm2
|
||||
; AVX1-NEXT: vpand %xmm2, %xmm0, %xmm2
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1,1,1,1,1,1,1,1]
|
||||
; AVX1-NEXT: vpsubw %xmm3, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm2, %xmm5
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
|
||||
; AVX1-NEXT: vpshufb %xmm5, %xmm6, %xmm5
|
||||
; AVX1-NEXT: vpsrlw $4, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpshufb %xmm2, %xmm5, %xmm2
|
||||
; AVX1-NEXT: vpaddb %xmm4, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpsllw $8, %xmm2, %xmm4
|
||||
; AVX1-NEXT: vpaddb %xmm2, %xmm4, %xmm2
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpshufb %xmm2, %xmm6, %xmm2
|
||||
; AVX1-NEXT: vpaddb %xmm5, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpsllw $8, %xmm2, %xmm5
|
||||
; AVX1-NEXT: vpaddb %xmm2, %xmm5, %xmm2
|
||||
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
|
||||
; AVX1-NEXT: vpsubw %xmm1, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm1
|
||||
; AVX1-NEXT: vpshufb %xmm1, %xmm5, %xmm1
|
||||
; AVX1-NEXT: vpsubw %xmm0, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpsubw %xmm3, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm1
|
||||
; AVX1-NEXT: vpshufb %xmm1, %xmm6, %xmm1
|
||||
; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm5, %xmm0
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm6, %xmm0
|
||||
; AVX1-NEXT: vpaddb %xmm1, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpsllw $8, %xmm0, %xmm1
|
||||
; AVX1-NEXT: vpaddb %xmm0, %xmm1, %xmm0
|
||||
@ -757,27 +751,26 @@ define <32 x i8> @testv32i8(<32 x i8> %in) nounwind {
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
|
||||
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpsubb %xmm1, %xmm2, %xmm1
|
||||
; AVX1-NEXT: vpsubb %xmm0, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
|
||||
; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
|
||||
; AVX1-NEXT: vpsubb %xmm2, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
|
||||
; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm4
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
|
||||
; AVX1-NEXT: vpshufb %xmm4, %xmm5, %xmm4
|
||||
; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpsubb %xmm1, %xmm2, %xmm3
|
||||
; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpshufb %xmm1, %xmm5, %xmm1
|
||||
; AVX1-NEXT: vpaddb %xmm4, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpsubb %xmm2, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm2
|
||||
; AVX1-NEXT: vpshufb %xmm2, %xmm5, %xmm2
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
|
||||
; AVX1-NEXT: vpsubb %xmm3, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm1, %xmm5
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
|
||||
; AVX1-NEXT: vpshufb %xmm5, %xmm6, %xmm5
|
||||
; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpshufb %xmm1, %xmm6, %xmm1
|
||||
; AVX1-NEXT: vpaddb %xmm5, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpsubb %xmm0, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpand %xmm2, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpsubb %xmm3, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm2
|
||||
; AVX1-NEXT: vpshufb %xmm2, %xmm6, %xmm2
|
||||
; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm5, %xmm0
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm6, %xmm0
|
||||
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
@ -870,27 +863,26 @@ define <32 x i8> @testv32i8u(<32 x i8> %in) nounwind {
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
|
||||
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpsubb %xmm1, %xmm2, %xmm1
|
||||
; AVX1-NEXT: vpsubb %xmm0, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
|
||||
; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
|
||||
; AVX1-NEXT: vpsubb %xmm2, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
|
||||
; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm4
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
|
||||
; AVX1-NEXT: vpshufb %xmm4, %xmm5, %xmm4
|
||||
; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpsubb %xmm1, %xmm2, %xmm3
|
||||
; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpshufb %xmm1, %xmm5, %xmm1
|
||||
; AVX1-NEXT: vpaddb %xmm4, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpsubb %xmm2, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm2
|
||||
; AVX1-NEXT: vpshufb %xmm2, %xmm5, %xmm2
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
|
||||
; AVX1-NEXT: vpsubb %xmm3, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm1, %xmm5
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
|
||||
; AVX1-NEXT: vpshufb %xmm5, %xmm6, %xmm5
|
||||
; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpshufb %xmm1, %xmm6, %xmm1
|
||||
; AVX1-NEXT: vpaddb %xmm5, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpsubb %xmm0, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpand %xmm2, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpsubb %xmm3, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm2
|
||||
; AVX1-NEXT: vpshufb %xmm2, %xmm6, %xmm2
|
||||
; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm5, %xmm0
|
||||
; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm6, %xmm0
|
||||
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
|
||||
Loading…
Reference in New Issue
Block a user