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https://github.com/RPCS3/llvm-mirror.git
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Convert vectors to fixed sized arrays and smallvectors. Eliminate use of getNode that takes a vector.
llvm-svn: 29609
This commit is contained in:
Chris Lattner
parent
7e905fba17
commit
2f9c4426fc
@ -754,7 +754,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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SSARegMap *RegMap = MF.getSSARegMap();
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std::vector<SDOperand> ArgValues;
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SmallVector<SDOperand, 8> ArgValues;
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SDOperand Root = Op.getOperand(0);
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unsigned ArgOffset = 24;
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@ -916,7 +916,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
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// Return the new list of results.
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std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
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Op.Val->value_end());
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return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues);
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return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
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}
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/// isCallCompatibleAddress - Return the immediate to use if the specified
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@ -1111,7 +1111,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
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NodeTys.push_back(MVT::Other); // Returns a chain
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NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
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std::vector<SDOperand> Ops;
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SmallVector<SDOperand, 8> Ops;
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unsigned CallOpc = PPCISD::CALL;
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// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
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@ -1127,12 +1127,8 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
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else {
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// Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
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// to do the call, we can't use PPCISD::CALL.
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Ops.push_back(Chain);
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Ops.push_back(Callee);
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if (InFlag.Val)
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Ops.push_back(InFlag);
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Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, Ops);
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SDOperand MTCTROps[] = {Chain, Callee, InFlag};
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Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0));
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InFlag = Chain.getValue(1);
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// Copy the callee address into R12 on darwin.
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@ -1142,7 +1138,6 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
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NodeTys.clear();
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NodeTys.push_back(MVT::Other);
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NodeTys.push_back(MVT::Flag);
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Ops.clear();
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Ops.push_back(Chain);
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CallOpc = PPCISD::BCTRL;
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Callee.Val = 0;
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@ -1162,10 +1157,11 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
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if (InFlag.Val)
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Ops.push_back(InFlag);
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Chain = DAG.getNode(CallOpc, NodeTys, Ops);
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Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
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InFlag = Chain.getValue(1);
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std::vector<SDOperand> ResultVals;
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SDOperand ResultVals[3];
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unsigned NumResults = 0;
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NodeTys.clear();
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// If the call has results, copy the values out of the ret val registers.
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@ -1175,27 +1171,31 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
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case MVT::i32:
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if (Op.Val->getValueType(1) == MVT::i32) {
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Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, InFlag).getValue(1);
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ResultVals.push_back(Chain.getValue(0));
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ResultVals[0] = Chain.getValue(0);
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Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32,
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Chain.getValue(2)).getValue(1);
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ResultVals.push_back(Chain.getValue(0));
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ResultVals[1] = Chain.getValue(0);
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NumResults = 2;
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NodeTys.push_back(MVT::i32);
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} else {
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Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
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ResultVals.push_back(Chain.getValue(0));
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ResultVals[0] = Chain.getValue(0);
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NumResults = 1;
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}
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NodeTys.push_back(MVT::i32);
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break;
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case MVT::i64:
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Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1);
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ResultVals.push_back(Chain.getValue(0));
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ResultVals[0] = Chain.getValue(0);
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NumResults = 1;
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NodeTys.push_back(MVT::i64);
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break;
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case MVT::f32:
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case MVT::f64:
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Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0),
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InFlag).getValue(1);
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ResultVals.push_back(Chain.getValue(0));
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ResultVals[0] = Chain.getValue(0);
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NumResults = 1;
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NodeTys.push_back(Op.Val->getValueType(0));
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break;
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case MVT::v4f32:
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@ -1204,7 +1204,8 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
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case MVT::v16i8:
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Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0),
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InFlag).getValue(1);
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ResultVals.push_back(Chain.getValue(0));
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ResultVals[0] = Chain.getValue(0);
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NumResults = 1;
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NodeTys.push_back(Op.Val->getValueType(0));
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break;
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}
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@ -1214,12 +1215,13 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
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NodeTys.push_back(MVT::Other);
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// If the function returns void, just return the chain.
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if (ResultVals.empty())
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if (NumResults == 1)
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return Chain;
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// Otherwise, merge everything together with a MERGE_VALUES node.
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ResultVals.push_back(Chain);
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SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, ResultVals);
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ResultVals[NumResults++] = Chain;
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SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
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ResultVals, NumResults);
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return Res.getValue(Op.ResNo);
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}
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@ -2069,14 +2071,15 @@ static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
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}
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// Create the PPCISD altivec 'dot' comparison node.
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std::vector<SDOperand> Ops;
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SDOperand Ops[] = {
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Op.getOperand(2), // LHS
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Op.getOperand(3), // RHS
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DAG.getConstant(CompareOpc, MVT::i32)
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};
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std::vector<MVT::ValueType> VTs;
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Ops.push_back(Op.getOperand(2)); // LHS
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Ops.push_back(Op.getOperand(3)); // RHS
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Ops.push_back(DAG.getConstant(CompareOpc, MVT::i32));
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VTs.push_back(Op.getOperand(2).getValueType());
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VTs.push_back(MVT::Flag);
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SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops);
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SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
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// Now that we have the comparison, emit a copy from the CR to a GPR.
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// This is flagged to the above dot comparison.
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@ -2376,12 +2379,13 @@ SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
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std::vector<MVT::ValueType> VTs;
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VTs.push_back(MVT::i32);
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VTs.push_back(MVT::Other);
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std::vector<SDOperand> Ops;
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Ops.push_back(Load.getOperand(0)); // Chain
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Ops.push_back(Load.getOperand(1)); // Ptr
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Ops.push_back(Load.getOperand(2)); // SrcValue
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Ops.push_back(DAG.getValueType(N->getValueType(0))); // VT
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SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops);
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SDOperand Ops[] = {
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Load.getOperand(0), // Chain
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Load.getOperand(1), // Ptr
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Load.getOperand(2), // SrcValue
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DAG.getValueType(N->getValueType(0)) // VT
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};
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SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
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// If this is an i16 load, insert the truncate.
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SDOperand ResVal = BSLoad;
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@ -2481,14 +2485,15 @@ SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
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bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
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// Create the PPCISD altivec 'dot' comparison node.
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std::vector<SDOperand> Ops;
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std::vector<MVT::ValueType> VTs;
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Ops.push_back(LHS.getOperand(2)); // LHS of compare
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Ops.push_back(LHS.getOperand(3)); // RHS of compare
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Ops.push_back(DAG.getConstant(CompareOpc, MVT::i32));
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SDOperand Ops[] = {
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LHS.getOperand(2), // LHS of compare
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LHS.getOperand(3), // RHS of compare
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DAG.getConstant(CompareOpc, MVT::i32)
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};
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VTs.push_back(LHS.getOperand(2).getValueType());
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VTs.push_back(MVT::Flag);
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SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops);
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SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
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// Unpack the result based on how the target uses it.
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unsigned CompOpc;
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