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AMDGPU: Split LDS vector loads
If properly aligned this could allow using ds_read_b64. llvm-svn: 253975
This commit is contained in:
Matt Arsenault
parent
1c34836bdc
commit
314bb34783
@ -1484,7 +1484,7 @@ SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
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if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
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Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
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Store->getValue().getValueType().isVector()) {
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return ScalarizeVectorStore(Op, DAG);
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return SplitVectorStore(Op, DAG);
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}
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EVT MemVT = Store->getMemoryVT();
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@ -1191,7 +1191,8 @@ SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
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break;
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// fall-through
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case AMDGPUAS::LOCAL_ADDRESS:
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return ScalarizeVectorLoad(Op, DAG);
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// If properly aligned, if we split we might be able to use ds_read_b64.
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return SplitVectorLoad(Op, DAG);
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}
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}
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@ -89,8 +89,13 @@ define void @simple_read2_v3f32_superreg_align4(float addrspace(1)* %out) #0 {
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}
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; CI-LABEL: {{^}}simple_read2_v4f32_superreg_align8:
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_W:[0-9]+]]:[[REG_Z:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}}
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; CI-DAG: ds_read2_b64 v{{\[}}[[REG_W:[0-9]+]]:[[REG_Z:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}}
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; FIXME: These moves shouldn't be necessary, it should be able to
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; store the same register if offset1 was the non-zero offset.
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; CI: v_mov_b32
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; CI: v_mov_b32
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; CI: buffer_store_dwordx4
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; CI: s_endpgm
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define void @simple_read2_v4f32_superreg_align8(<4 x float> addrspace(1)* %out) #0 {
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@ -103,8 +108,9 @@ define void @simple_read2_v4f32_superreg_align8(<4 x float> addrspace(1)* %out)
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}
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; CI-LABEL: {{^}}simple_read2_v4f32_superreg:
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_W:[0-9]+]]:[[REG_Z:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}}
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; CI: ds_read2_b64 v{{\[}}[[REG_W:[0-9]+]]:[[REG_Z:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}}
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; CI: v_mov_b32
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; CI: v_mov_b32
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; CI: buffer_store_dwordx4
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; CI: s_endpgm
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define void @simple_read2_v4f32_superreg(<4 x float> addrspace(1)* %out) #0 {
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@ -118,13 +124,11 @@ define void @simple_read2_v4f32_superreg(<4 x float> addrspace(1)* %out) #0 {
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; FIXME: Extra moves shuffling superregister
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; CI-LABEL: {{^}}simple_read2_v8f32_superreg:
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT3:[0-9]+]]:[[REG_ELT7:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:3 offset1:7{{$}}
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; CI: ds_read2_b64 v{{\[}}[[REG_ELT3:[0-9]+]]:[[REG_ELT7:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1 offset1:3{{$}}
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; CI: v_mov_b32
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT6:[0-9]+]]:[[REG_ELT5:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:2 offset1:1{{$}}
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; CI: v_mov_b32
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT4:[0-9]+]]:[[REG_ELT2:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:6 offset1:5{{$}}
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; CI: ds_read2_b64 v{{\[}}[[REG_ELT6:[0-9]+]]:[[REG_ELT5:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:2{{$}}
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; CI: v_mov_b32
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT1:[0-9]+]]:[[REG_ELT0:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:4{{$}}
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; CI: v_mov_b32
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; CI: buffer_store_dwordx4
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; CI: buffer_store_dwordx4
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@ -140,21 +144,15 @@ define void @simple_read2_v8f32_superreg(<8 x float> addrspace(1)* %out) #0 {
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; FIXME: Extra moves shuffling superregister
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; CI-LABEL: {{^}}simple_read2_v16f32_superreg:
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT11:[0-9]+]]:[[REG_ELT15:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:3 offset1:7{{$}}
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; CI: ds_read2_b64 v{{\[}}[[REG_ELT11:[0-9]+]]:[[REG_ELT15:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1 offset1:3{{$}}
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; CI: v_mov_b32
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT14:[0-9]+]]:[[REG_ELT13:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:11 offset1:15{{$}}
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; CI: v_mov_b32
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT12:[0-9]+]]:[[REG_ELT10:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:2 offset1:1{{$}}
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; CI: ds_read2_b64 v{{\[}}[[REG_ELT14:[0-9]+]]:[[REG_ELT13:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:5 offset1:7{{$}}
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; CI: ds_read2_b64 v{{\[}}[[REG_ELT14:[0-9]+]]:[[REG_ELT13:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:6 offset1:4{{$}}
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; CI: v_mov_b32
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT9:[0-9]+]]:[[REG_ELT8:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:6 offset1:5{{$}}
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; CI: v_mov_b32
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:10 offset1:9{{$}}
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; CI: ds_read2_b64 v{{\[}}[[REG_ELT12:[0-9]+]]:[[REG_ELT10:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:2{{$}}
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; CI: v_mov_b32
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT5:[0-9]+]]:[[REG_ELT4:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:14 offset1:13{{$}}
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; CI: v_mov_b32
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT3:[0-9]+]]:[[REG_ELT2:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:12 offset1:8{{$}}
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; CI: v_mov_b32
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT1:[0-9]+]]:[[REG_ELT0:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:4{{$}}
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; CI: v_mov_b32
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; CI: s_waitcnt lgkmcnt(0)
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@ -29,14 +29,10 @@ define void @private_access_f64_alloca(double addrspace(1)* noalias %out, double
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; SI-ALLOCA: buffer_store_dwordx4
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; SI-ALLOCA: buffer_load_dwordx4
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; SI-PROMOTE: ds_write_b32
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; SI-PROMOTE: ds_write_b32
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; SI-PROMOTE: ds_write_b32
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; SI-PROMOTE: ds_write_b32
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; SI-PROMOTE: ds_read_b32
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; SI-PROMOTE: ds_read_b32
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; SI-PROMOTE: ds_read_b32
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; SI-PROMOTE: ds_read_b32
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; SI-PROMOTE: ds_write_b64
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; SI-PROMOTE: ds_write_b64
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; SI-PROMOTE: ds_read_b64
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; SI-PROMOTE: ds_read_b64
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define void @private_access_v2f64_alloca(<2 x double> addrspace(1)* noalias %out, <2 x double> addrspace(1)* noalias %in, i32 %b) nounwind {
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%val = load <2 x double>, <2 x double> addrspace(1)* %in, align 16
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%array = alloca <2 x double>, i32 16, align 16
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@ -71,14 +67,10 @@ define void @private_access_i64_alloca(i64 addrspace(1)* noalias %out, i64 addrs
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; SI-ALLOCA: buffer_store_dwordx4
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; SI-ALLOCA: buffer_load_dwordx4
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; SI-PROMOTE: ds_write_b32
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; SI-PROMOTE: ds_write_b32
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; SI-PROMOTE: ds_write_b32
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; SI-PROMOTE: ds_write_b32
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; SI-PROMOTE: ds_read_b32
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; SI-PROMOTE: ds_read_b32
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; SI-PROMOTE: ds_read_b32
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; SI-PROMOTE: ds_read_b32
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; SI-PROMOTE: ds_write_b64
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; SI-PROMOTE: ds_write_b64
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; SI-PROMOTE: ds_read_b64
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; SI-PROMOTE: ds_read_b64
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define void @private_access_v2i64_alloca(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %in, i32 %b) nounwind {
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%val = load <2 x i64>, <2 x i64> addrspace(1)* %in, align 16
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%array = alloca <2 x i64>, i32 16, align 16
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@ -132,32 +132,15 @@ define void @test_small_memcpy_i64_lds_to_lds_align2(i64 addrspace(3)* noalias %
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}
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; FUNC-LABEL: {{^}}test_small_memcpy_i64_lds_to_lds_align4:
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; SI-DAG: ds_read_b32
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; SI-DAG: ds_write_b32
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; SI: ds_read2_b32
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; SI: ds_read2_b32
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; SI: ds_read2_b32
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; SI: ds_read2_b32
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; SI-DAG: ds_read_b32
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; SI-DAG: ds_write_b32
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; SI-DAG: ds_read_b32
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; SI-DAG: ds_write_b32
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; SI-DAG: ds_read_b32
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; SI-DAG: ds_write_b32
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; SI-DAG: ds_read_b32
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; SI-DAG: ds_write_b32
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; SI-DAG: ds_read_b32
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; SI-DAG: ds_write_b32
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; SI-DAG: ds_read_b32
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; SI-DAG: ds_write_b32
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; SI-DAG: ds_read_b32
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; SI-DAG: ds_write_b32
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; SI-DAG: ds_read_b32
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; SI-DAG: ds_write_b32
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; SI: ds_write2_b32
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; SI: ds_write2_b32
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; SI: ds_write2_b32
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; SI: ds_write2_b32
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; SI: s_endpgm
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define void @test_small_memcpy_i64_lds_to_lds_align4(i64 addrspace(3)* noalias %out, i64 addrspace(3)* noalias %in) nounwind {
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@ -170,32 +153,15 @@ define void @test_small_memcpy_i64_lds_to_lds_align4(i64 addrspace(3)* noalias %
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; FIXME: Use 64-bit ops
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; FUNC-LABEL: {{^}}test_small_memcpy_i64_lds_to_lds_align8:
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; SI-DAG: ds_read_b32
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; SI-DAG: ds_write_b32
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; SI: ds_read_b64
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; SI: ds_read_b64
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; SI: ds_read_b64
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; SI: ds_read_b64
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; SI-DAG: ds_read_b32
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; SI-DAG: ds_write_b32
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; SI-DAG: ds_read_b32
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; SI-DAG: ds_write_b32
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; SI-DAG: ds_read_b32
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; SI-DAG: ds_write_b32
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; SI-DAG: ds_read_b32
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; SI-DAG: ds_write_b32
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; SI-DAG: ds_read_b32
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; SI-DAG: ds_write_b32
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; SI-DAG: ds_read_b32
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; SI-DAG: ds_write_b32
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; SI-DAG: ds_read_b32
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; SI-DAG: ds_write_b32
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; SI-DAG: ds_read_b32
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; SI-DAG: ds_write_b32
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; SI: ds_write_b64
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; SI: ds_write_b64
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; SI: ds_write_b64
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; SI: ds_write_b64
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; SI-DAG: s_endpgm
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define void @test_small_memcpy_i64_lds_to_lds_align8(i64 addrspace(3)* noalias %out, i64 addrspace(3)* noalias %in) nounwind {
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@ -539,10 +539,15 @@ define void @merge_local_store_2_constants_i32(i32 addrspace(3)* %out) #0 {
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}
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; GCN-LABEL: {{^}}merge_local_store_4_constants_i32:
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; GCN: ds_write_b32
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; GCN: ds_write_b32
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; GCN: ds_write_b32
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; GCN: ds_write_b32
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; GCN-DAG: v_mov_b32_e32 [[K2:v[0-9]+]], 0x1c8
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; GCN-DAG: v_mov_b32_e32 [[K3:v[0-9]+]], 0x14d
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; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, [[K2]], [[K3]] offset0:2 offset1:3
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; GCN-DAG: v_mov_b32_e32 [[K0:v[0-9]+]], 0x4d2
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; GCN-DAG: v_mov_b32_e32 [[K1:v[0-9]+]], 0x7b
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; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, [[K0]], [[K1]] offset1:1
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; GCN: s_endpgm
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define void @merge_local_store_4_constants_i32(i32 addrspace(3)* %out) #0 {
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%out.gep.1 = getelementptr i32, i32 addrspace(3)* %out, i32 1
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%out.gep.2 = getelementptr i32, i32 addrspace(3)* %out, i32 2
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@ -287,16 +287,33 @@ entry:
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; CM: LDS_WRITE
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; CM: LDS_WRITE
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; SI: ds_write_b32
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; SI: ds_write_b32
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; SI: ds_write_b32
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; SI: ds_write_b32
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; SI: ds_write_b64
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; SI: ds_write_b64
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define void @store_local_v4i32(<4 x i32> addrspace(3)* %out, <4 x i32> %in) {
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entry:
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store <4 x i32> %in, <4 x i32> addrspace(3)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}store_local_v4i32_align4:
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; EG: LDS_WRITE
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; EG: LDS_WRITE
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; EG: LDS_WRITE
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; EG: LDS_WRITE
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; CM: LDS_WRITE
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; CM: LDS_WRITE
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; CM: LDS_WRITE
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; CM: LDS_WRITE
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; SI: ds_write2_b32
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; SI: ds_write2_b32
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define void @store_local_v4i32_align4(<4 x i32> addrspace(3)* %out, <4 x i32> %in) {
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entry:
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store <4 x i32> %in, <4 x i32> addrspace(3)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}store_local_i64_i8:
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; EG: LDS_BYTE_WRITE
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; SI: ds_write_b8
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