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Switch some multiplication instructions over to the new scheme for testing.

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llvm-svn: 40723
This commit is contained in:
Evan Cheng 2007-08-02 05:48:35 +00:00
parent a06b9cf09f
commit 3163814591
2 changed files with 53 additions and 12 deletions
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53
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -1045,6 +1045,50 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
break; break;
} }
case ISD::MUL: {
if (NVT == MVT::i8) {
SDOperand N0 = Node->getOperand(0);
SDOperand N1 = Node->getOperand(1);
SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
if (!foldedLoad) {
foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3);
if (foldedLoad)
std::swap(N0, N1);
}
SDNode *ResNode;
if (foldedLoad) {
SDOperand Chain = N1.getOperand(0);
AddToISelQueue(N0);
AddToISelQueue(Chain);
AddToISelQueue(Tmp0);
AddToISelQueue(Tmp1);
AddToISelQueue(Tmp2);
AddToISelQueue(Tmp3);
SDOperand InFlag(0, 0);
Chain = CurDAG->getCopyToReg(Chain, X86::AL, N0, InFlag);
InFlag = Chain.getValue(1);
SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Chain, InFlag };
ResNode = CurDAG->getTargetNode(X86::MUL8m, MVT::i8, MVT::i8,
MVT::Other, Ops, 6);
ReplaceUses(N1.getValue(1), SDOperand(ResNode, 2));
} else {
SDOperand Chain = CurDAG->getEntryNode();
AddToISelQueue(N0);
AddToISelQueue(N1);
SDOperand InFlag(0, 0);
InFlag = CurDAG->getCopyToReg(Chain, X86::AL, N0, InFlag).getValue(1);
ResNode = CurDAG->getTargetNode(X86::MUL8r, MVT::i8, MVT::i8,
N1, InFlag);
}
ReplaceUses(N.getValue(0), SDOperand(ResNode, 0));
return NULL;
}
break;
}
case ISD::MULHU: case ISD::MULHU:
case ISD::MULHS: { case ISD::MULHS: {
if (Opcode == ISD::MULHU) if (Opcode == ISD::MULHU)
@ -1076,16 +1120,13 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
SDOperand N0 = Node->getOperand(0); SDOperand N0 = Node->getOperand(0);
SDOperand N1 = Node->getOperand(1); SDOperand N1 = Node->getOperand(1);
bool foldedLoad = false;
SDOperand Tmp0, Tmp1, Tmp2, Tmp3; SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3); bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
// MULHU and MULHS are commmutative // MULHU and MULHS are commmutative
if (!foldedLoad) { if (!foldedLoad) {
foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3); foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3);
if (foldedLoad) { if (foldedLoad)
N0 = Node->getOperand(1); std::swap(N0, N1);
N1 = Node->getOperand(0);
}
} }
SDOperand Chain; SDOperand Chain;

10
lib/Target/X86/X86InstrInfo.td
View File

@ -548,7 +548,7 @@ def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
// FIXME: Used for 8-bit mul, ignore result upper 8 bits. // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
// This probably ought to be moved to a def : Pat<> if the // This probably ought to be moved to a def : Pat<> if the
// syntax can be accepted. // syntax can be accepted.
[(set AL, (mul AL, GR8:$src))]>, []>,
Imp<[AL],[AL,AH]>; // AL,AH = AL*GR8 Imp<[AL],[AL,AH]>; // AL,AH = AL*GR8
def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w}\t$src", []>, def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w}\t$src", []>,
Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16
@ -559,8 +559,8 @@ def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
// FIXME: Used for 8-bit mul, ignore result upper 8 bits. // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
// This probably ought to be moved to a def : Pat<> if the // This probably ought to be moved to a def : Pat<> if the
// syntax can be accepted. // syntax can be accepted.
[(set AL, (mul AL, (loadi8 addr:$src)))]>, []>,
Imp<[AL],[AX]>; // AL,AH = AL*[mem8] Imp<[AL],[AL,AH]>; // AL,AH = AL*[mem8]
def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src), def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
"mul{w}\t$src", []>, Imp<[AX],[AX,DX]>, "mul{w}\t$src", []>, Imp<[AX],[AX,DX]>,
OpSize; // AX,DX = AX*[mem16] OpSize; // AX,DX = AX*[mem16]
@ -568,13 +568,13 @@ def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
"mul{l}\t$src", []>, Imp<[EAX],[EAX,EDX]>;// EAX,EDX = EAX*[mem32] "mul{l}\t$src", []>, Imp<[EAX],[EAX,EDX]>;// EAX,EDX = EAX*[mem32]
def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>, def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>,
Imp<[AL],[AX]>; // AL,AH = AL*GR8 Imp<[AL],[AL,AH]>; // AL,AH = AL*GR8
def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>, def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16
def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>, def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>,
Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*GR32 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*GR32
def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src), def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
"imul{b}\t$src", []>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8] "imul{b}\t$src", []>, Imp<[AL],[AL,AH]>; // AL,AH = AL*[mem8]
def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src), def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
"imul{w}\t$src", []>, Imp<[AX],[AX,DX]>, "imul{w}\t$src", []>, Imp<[AX],[AX,DX]>,
OpSize; // AX,DX = AX*[mem16] OpSize; // AX,DX = AX*[mem16]