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https://github.com/RPCS3/llvm-mirror.git
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Refactor code to select NEON VST intrinsics.
llvm-svn: 84122
This commit is contained in:
Bob Wilson
parent
89ef6dcb54
commit
320891060f
@ -133,6 +133,13 @@ private:
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SDNode *SelectVLD(SDValue Op, unsigned NumVecs, unsigned *DOpcodes,
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unsigned *QOpcodes0, unsigned *QOpcodes1);
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/// SelectVST - Select NEON store intrinsics. NumVecs should
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/// be 2, 3 or 4. The opcode arrays specify the instructions used for
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/// stores of D registers and even subregs and odd subregs of Q registers.
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/// For NumVecs == 2, QOpcodes1 is not used.
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SDNode *SelectVST(SDValue Op, unsigned NumVecs, unsigned *DOpcodes,
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unsigned *QOpcodes0, unsigned *QOpcodes1);
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/// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
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/// be 2, 3 or 4. The opcode arrays specify the instructions used for
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/// load/store of D registers and even subregs and odd subregs of Q registers.
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@ -1063,13 +1070,13 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDValue Op, unsigned NumVecs,
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ResTys.push_back(MemAddr.getValueType());
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ResTys.push_back(MVT::Other);
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// Load the even subreg.
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// Load the even subregs.
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unsigned Opc = QOpcodes0[OpcodeIndex];
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const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, Chain };
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SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 4);
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Chain = SDValue(VLdA, NumVecs+1);
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// Load the odd subreg.
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// Load the odd subregs.
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Opc = QOpcodes1[OpcodeIndex];
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const SDValue OpsB[] = { SDValue(VLdA, NumVecs), MemUpdate, MemOpc, Chain };
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SDNode *VLdB = CurDAG->getMachineNode(Opc, dl, ResTys, OpsB, 4);
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@ -1085,6 +1092,95 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDValue Op, unsigned NumVecs,
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return NULL;
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}
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SDNode *ARMDAGToDAGISel::SelectVST(SDValue Op, unsigned NumVecs,
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unsigned *DOpcodes, unsigned *QOpcodes0,
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unsigned *QOpcodes1) {
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assert(NumVecs >=2 && NumVecs <= 4 && "VST NumVecs out-of-range");
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SDNode *N = Op.getNode();
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DebugLoc dl = N->getDebugLoc();
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
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return NULL;
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SDValue Chain = N->getOperand(0);
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EVT VT = N->getOperand(3).getValueType();
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bool is64BitVector = VT.is64BitVector();
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unsigned OpcodeIndex;
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vst type");
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// Double-register operations:
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case MVT::v8i8: OpcodeIndex = 0; break;
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case MVT::v4i16: OpcodeIndex = 1; break;
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case MVT::v2f32:
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case MVT::v2i32: OpcodeIndex = 2; break;
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case MVT::v1i64: OpcodeIndex = 3; break;
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// Quad-register operations:
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case MVT::v16i8: OpcodeIndex = 0; break;
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case MVT::v8i16: OpcodeIndex = 1; break;
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case MVT::v4f32:
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case MVT::v4i32: OpcodeIndex = 2; break;
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}
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SmallVector<SDValue, 8> Ops;
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Ops.push_back(MemAddr);
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Ops.push_back(MemUpdate);
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Ops.push_back(MemOpc);
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if (is64BitVector) {
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unsigned Opc = DOpcodes[OpcodeIndex];
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for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
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Ops.push_back(N->getOperand(Vec+3));
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Ops.push_back(Chain);
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return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+4);
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}
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EVT RegVT = GetNEONSubregVT(VT);
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if (NumVecs == 2) {
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// Quad registers are directly supported for VST2,
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// storing 2 pairs of D regs.
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unsigned Opc = QOpcodes0[OpcodeIndex];
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for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
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N->getOperand(Vec+3)));
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
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N->getOperand(Vec+3)));
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}
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Ops.push_back(Chain);
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return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 8);
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}
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// Otherwise, quad registers are stored with two separate instructions,
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// where one stores the even registers and the other stores the odd registers.
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// Enable writeback to the address register.
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MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
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// Store the even subregs.
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for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
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N->getOperand(Vec+3)));
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Ops.push_back(Chain);
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unsigned Opc = QOpcodes0[OpcodeIndex];
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SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
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MVT::Other, Ops.data(), NumVecs+4);
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Chain = SDValue(VStA, 1);
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// Store the odd subregs.
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Ops[0] = SDValue(VStA, 0); // MemAddr
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for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
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Ops[Vec+3] = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
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N->getOperand(Vec+3));
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Ops[NumVecs+3] = Chain;
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Opc = QOpcodes1[OpcodeIndex];
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SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
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MVT::Other, Ops.data(), NumVecs+4);
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Chain = SDValue(VStB, 1);
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ReplaceUses(SDValue(N, 0), Chain);
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return NULL;
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}
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SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDValue Op, bool IsLoad,
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unsigned NumVecs, unsigned *DOpcodes,
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unsigned *QOpcodes0,
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@ -1664,178 +1760,26 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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}
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case Intrinsic::arm_neon_vst2: {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
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return NULL;
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SDValue Chain = N->getOperand(0);
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VT = N->getOperand(3).getValueType();
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if (VT.is64BitVector()) {
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vst2 type");
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case MVT::v8i8: Opc = ARM::VST2d8; break;
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case MVT::v4i16: Opc = ARM::VST2d16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VST2d32; break;
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case MVT::v1i64: Opc = ARM::VST2d64; break;
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}
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
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N->getOperand(3), N->getOperand(4), Chain };
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return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 6);
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}
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// Quad registers are stored as pairs of double registers.
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EVT RegVT;
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vst2 type");
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case MVT::v16i8: Opc = ARM::VST2q8; RegVT = MVT::v8i8; break;
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case MVT::v8i16: Opc = ARM::VST2q16; RegVT = MVT::v4i16; break;
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case MVT::v4f32: Opc = ARM::VST2q32; RegVT = MVT::v2f32; break;
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case MVT::v4i32: Opc = ARM::VST2q32; RegVT = MVT::v2i32; break;
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}
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SDValue D0 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
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N->getOperand(3));
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SDValue D1 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
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N->getOperand(3));
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SDValue D2 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
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N->getOperand(4));
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SDValue D3 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
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N->getOperand(4));
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
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D0, D1, D2, D3, Chain };
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return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 8);
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unsigned DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
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ARM::VST2d32, ARM::VST2d64 };
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unsigned QOpcodes[] = { ARM::VST2q8, ARM::VST2q16, ARM::VST2q32 };
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return SelectVST(Op, 2, DOpcodes, QOpcodes, 0);
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}
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case Intrinsic::arm_neon_vst3: {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
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return NULL;
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SDValue Chain = N->getOperand(0);
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VT = N->getOperand(3).getValueType();
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if (VT.is64BitVector()) {
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vst3 type");
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case MVT::v8i8: Opc = ARM::VST3d8; break;
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case MVT::v4i16: Opc = ARM::VST3d16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VST3d32; break;
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case MVT::v1i64: Opc = ARM::VST3d64; break;
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}
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
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N->getOperand(3), N->getOperand(4),
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N->getOperand(5), Chain };
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return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7);
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}
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// Quad registers are stored with two separate instructions, where one
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// stores the even registers and the other stores the odd registers.
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EVT RegVT;
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unsigned Opc2 = 0;
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vst3 type");
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case MVT::v16i8:
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Opc = ARM::VST3q8a; Opc2 = ARM::VST3q8b; RegVT = MVT::v8i8; break;
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case MVT::v8i16:
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Opc = ARM::VST3q16a; Opc2 = ARM::VST3q16b; RegVT = MVT::v4i16; break;
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case MVT::v4f32:
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Opc = ARM::VST3q32a; Opc2 = ARM::VST3q32b; RegVT = MVT::v2f32; break;
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case MVT::v4i32:
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Opc = ARM::VST3q32a; Opc2 = ARM::VST3q32b; RegVT = MVT::v2i32; break;
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}
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// Enable writeback to the address register.
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MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
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SDValue D0 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
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N->getOperand(3));
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SDValue D2 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
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N->getOperand(4));
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SDValue D4 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
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N->getOperand(5));
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const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, D0, D2, D4, Chain };
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SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
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MVT::Other, OpsA, 7);
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Chain = SDValue(VStA, 1);
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SDValue D1 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
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N->getOperand(3));
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SDValue D3 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
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N->getOperand(4));
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SDValue D5 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
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N->getOperand(5));
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MemAddr = SDValue(VStA, 0);
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const SDValue OpsB[] = { MemAddr, MemUpdate, MemOpc, D1, D3, D5, Chain };
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SDNode *VStB = CurDAG->getMachineNode(Opc2, dl, MemAddr.getValueType(),
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MVT::Other, OpsB, 7);
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Chain = SDValue(VStB, 1);
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ReplaceUses(SDValue(N, 0), Chain);
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return NULL;
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unsigned DOpcodes[] = { ARM::VST3d8, ARM::VST3d16,
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ARM::VST3d32, ARM::VST3d64 };
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unsigned QOpcodes0[] = { ARM::VST3q8a, ARM::VST3q16a, ARM::VST3q32a };
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unsigned QOpcodes1[] = { ARM::VST3q8b, ARM::VST3q16b, ARM::VST3q32b };
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return SelectVST(Op, 3, DOpcodes, QOpcodes0, QOpcodes1);
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}
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case Intrinsic::arm_neon_vst4: {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
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return NULL;
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SDValue Chain = N->getOperand(0);
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VT = N->getOperand(3).getValueType();
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if (VT.is64BitVector()) {
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vst4 type");
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case MVT::v8i8: Opc = ARM::VST4d8; break;
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case MVT::v4i16: Opc = ARM::VST4d16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VST4d32; break;
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case MVT::v1i64: Opc = ARM::VST4d64; break;
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}
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
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N->getOperand(3), N->getOperand(4),
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N->getOperand(5), N->getOperand(6), Chain };
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return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 8);
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}
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// Quad registers are stored with two separate instructions, where one
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// stores the even registers and the other stores the odd registers.
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EVT RegVT;
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unsigned Opc2 = 0;
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vst4 type");
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case MVT::v16i8:
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Opc = ARM::VST4q8a; Opc2 = ARM::VST4q8b; RegVT = MVT::v8i8; break;
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case MVT::v8i16:
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Opc = ARM::VST4q16a; Opc2 = ARM::VST4q16b; RegVT = MVT::v4i16; break;
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case MVT::v4f32:
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Opc = ARM::VST4q32a; Opc2 = ARM::VST4q32b; RegVT = MVT::v2f32; break;
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case MVT::v4i32:
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Opc = ARM::VST4q32a; Opc2 = ARM::VST4q32b; RegVT = MVT::v2i32; break;
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}
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// Enable writeback to the address register.
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MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
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SDValue D0 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
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N->getOperand(3));
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SDValue D2 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
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N->getOperand(4));
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SDValue D4 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
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N->getOperand(5));
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SDValue D6 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
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N->getOperand(6));
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const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc,
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D0, D2, D4, D6, Chain };
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SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
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MVT::Other, OpsA, 8);
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Chain = SDValue(VStA, 1);
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SDValue D1 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
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N->getOperand(3));
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SDValue D3 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
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N->getOperand(4));
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SDValue D5 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
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N->getOperand(5));
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SDValue D7 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
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N->getOperand(6));
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MemAddr = SDValue(VStA, 0);
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const SDValue OpsB[] = { MemAddr, MemUpdate, MemOpc,
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D1, D3, D5, D7, Chain };
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SDNode *VStB = CurDAG->getMachineNode(Opc2, dl, MemAddr.getValueType(),
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MVT::Other, OpsB, 8);
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Chain = SDValue(VStB, 1);
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ReplaceUses(SDValue(N, 0), Chain);
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return NULL;
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unsigned DOpcodes[] = { ARM::VST4d8, ARM::VST4d16,
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ARM::VST4d32, ARM::VST4d64 };
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unsigned QOpcodes0[] = { ARM::VST4q8a, ARM::VST4q16a, ARM::VST4q32a };
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unsigned QOpcodes1[] = { ARM::VST4q8b, ARM::VST4q16b, ARM::VST4q32b };
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return SelectVST(Op, 4, DOpcodes, QOpcodes0, QOpcodes1);
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}
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case Intrinsic::arm_neon_vst2lane: {
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