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[X86][SSE] Add additional PR40318 shuffle test cases
llvm-svn: 351333
This commit is contained in:
Simon Pilgrim
parent
7d67e5d0c6
commit
326457e304
@ -1532,6 +1532,111 @@ define <16 x i8> @shuffle_v16i8_07_zz_zz_zz_zz_zz_uu_uu_15_uu_uu_uu_uu_uu_zz_zz(
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ret <16 x i8> %shuffle
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}
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define <16 x i8> @shuffle_v16i8_zz_zz_zz_zz_01_02_03_04_05_06_zz_zz_zz_zz_zz_zz(<16 x i8> %a) {
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; SSE2-LABEL: shuffle_v16i8_zz_zz_zz_zz_01_02_03_04_05_06_zz_zz_zz_zz_zz_zz:
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; SSE2: # %bb.0:
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; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE2-NEXT: pxor %xmm1, %xmm1
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; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
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; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm0[0,1,2,3,6,5,6,7]
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,0,3]
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; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[3,2,0,0,4,5,6,7]
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; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,4,4,4]
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,0]
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; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,7,6,7]
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,3,2,1]
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; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[2,2,2,2,4,5,6,7]
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; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,6,7,4]
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; SSE2-NEXT: packuswb %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: shuffle_v16i8_zz_zz_zz_zz_01_02_03_04_05_06_zz_zz_zz_zz_zz_zz:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[1,2,3,4,5,6],zero,zero,zero,zero,zero,zero
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: shuffle_v16i8_zz_zz_zz_zz_01_02_03_04_05_06_zz_zz_zz_zz_zz_zz:
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; SSE41: # %bb.0:
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; SSE41-NEXT: pshufb {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[1,2,3,4,5,6],zero,zero,zero,zero,zero,zero
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: shuffle_v16i8_zz_zz_zz_zz_01_02_03_04_05_06_zz_zz_zz_zz_zz_zz:
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; AVX: # %bb.0:
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; AVX-NEXT: vpshufb {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[1,2,3,4,5,6],zero,zero,zero,zero,zero,zero
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; AVX-NEXT: retq
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
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ret <16 x i8> %shuffle
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}
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define <16 x i8> @shuffle_v16i8_01_02_03_04_05_06_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz(<16 x i8> %a) {
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; SSE2-LABEL: shuffle_v16i8_01_02_03_04_05_06_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
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; SSE2: # %bb.0:
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; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE2-NEXT: pxor %xmm1, %xmm1
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; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
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; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,0,2,3,4,5,6,7]
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,0]
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; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,6,5,4,7]
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,0]
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; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,2,3,0,4,5,6,7]
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; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,6,4,4]
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; SSE2-NEXT: packuswb %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: shuffle_v16i8_01_02_03_04_05_06_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: shuffle_v16i8_01_02_03_04_05_06_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
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; SSE41: # %bb.0:
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; SSE41-NEXT: pshufb {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: shuffle_v16i8_01_02_03_04_05_06_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
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; AVX: # %bb.0:
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; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
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; AVX-NEXT: retq
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <16 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
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ret <16 x i8> %shuffle
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}
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define <16 x i8> @shuffle_v16i8_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_01_02_03_04_05_06(<16 x i8> %a) {
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; SSE2-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_01_02_03_04_05_06:
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; SSE2: # %bb.0:
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; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE2-NEXT: pxor %xmm1, %xmm1
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; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
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; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,0,2,3,4,5,6,7]
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,0]
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; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,3,2,3,4,5,6,7]
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,0]
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; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,1,2,4,5,6,7]
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; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,4,5,6]
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; SSE2-NEXT: packuswb %xmm0, %xmm1
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; SSE2-NEXT: movdqa %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_01_02_03_04_05_06:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[1,2,3,4,5,6]
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_01_02_03_04_05_06:
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; SSE41: # %bb.0:
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; SSE41-NEXT: pshufb {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[1,2,3,4,5,6]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_01_02_03_04_05_06:
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; AVX: # %bb.0:
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; AVX-NEXT: vpshufb {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[1,2,3,4,5,6]
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; AVX-NEXT: retq
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>
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ret <16 x i8> %shuffle
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}
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define <16 x i8> @PR12412(<16 x i8> %inval1, <16 x i8> %inval2) {
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; SSE2-LABEL: PR12412:
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; SSE2: # %bb.0: # %entry
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@ -2535,6 +2535,55 @@ define <8 x i16> @shuffle_v8i16_2zzzuuuu(<8 x i16> %x) {
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ret <8 x i16> %r
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}
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define <8 x i16> @shuffle_v8i16_3uu6zzzz(<8 x i16> %x) {
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; SSE2-LABEL: shuffle_v8i16_3uu6zzzz:
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; SSE2: # %bb.0:
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; SSE2-NEXT: psrldq {{.*#+}} xmm0 = xmm0[6,7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero
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; SSE2-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: shuffle_v8i16_3uu6zzzz:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[6,7,u,u,u,u,12,13],zero,zero,zero,zero,zero,zero,zero,zero
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: shuffle_v8i16_3uu6zzzz:
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; SSE41: # %bb.0:
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; SSE41-NEXT: psrldq {{.*#+}} xmm0 = xmm0[6,7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero
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; SSE41-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
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; SSE41-NEXT: retq
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;
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; AVX1-LABEL: shuffle_v8i16_3uu6zzzz:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[6,7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero
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; AVX1-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
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; AVX1-NEXT: retq
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;
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; AVX2-SLOW-LABEL: shuffle_v8i16_3uu6zzzz:
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; AVX2-SLOW: # %bb.0:
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; AVX2-SLOW-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[6,7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero
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; AVX2-SLOW-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
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; AVX2-SLOW-NEXT: retq
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;
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; AVX2-FAST-LABEL: shuffle_v8i16_3uu6zzzz:
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; AVX2-FAST: # %bb.0:
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; AVX2-FAST-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[6,7,8,9,10,11,12,13],zero,zero,zero,zero,zero,zero,zero,zero
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; AVX2-FAST-NEXT: retq
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;
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; AVX512VL-SLOW-LABEL: shuffle_v8i16_3uu6zzzz:
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; AVX512VL-SLOW: # %bb.0:
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; AVX512VL-SLOW-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[6,7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero
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; AVX512VL-SLOW-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
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; AVX512VL-SLOW-NEXT: retq
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;
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; AVX512VL-FAST-LABEL: shuffle_v8i16_3uu6zzzz:
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; AVX512VL-FAST: # %bb.0:
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; AVX512VL-FAST-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[6,7,8,9,10,11,12,13],zero,zero,zero,zero,zero,zero,zero,zero
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; AVX512VL-FAST-NEXT: retq
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%r = shufflevector <8 x i16> %x, <8 x i16> zeroinitializer, <8 x i32> <i32 3, i32 undef, i32 undef, i32 6, i32 8, i32 8, i32 8, i32 8>
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ret <8 x i16> %r
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}
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define <8 x i16> @mask_v8i16_012345ef(<8 x i16> %a, <8 x i16> %b) {
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; SSE2-LABEL: mask_v8i16_012345ef:
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; SSE2: # %bb.0:
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