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[MachineVerifier] retrofit iterators with range for. NFC
Summary: Reviewing failures identified in D78586, I was finding the identifiers for these iterators hard to read. Reviewers: efriedma, MaskRay, jyknight Reviewed By: MaskRay Subscribers: hiraditya, llvm-commits, srhines Tags: #llvm Differential Revision: https://reviews.llvm.org/D78849
This commit is contained in:
Nick Desaulniers
parent
eeedbd9928
commit
32b2707dc3
@ -168,20 +168,14 @@ namespace {
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// Same for a full set.
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bool addRequired(const RegSet &RS) {
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bool changed = false;
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for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
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if (addRequired(*I))
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changed = true;
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return changed;
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return llvm::any_of(RS,
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[this](unsigned Reg) { return addRequired(Reg); });
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}
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// Same for a full map.
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bool addRequired(const RegMap &RM) {
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bool changed = false;
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for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
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if (addRequired(I->first))
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changed = true;
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return changed;
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return llvm::any_of(
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RM, [this](const auto &P) { return addRequired(P.first); });
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}
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// Live-out registers are either in regsLiveOut or vregsPassed.
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@ -379,43 +373,40 @@ unsigned MachineVerifier::verify(MachineFunction &MF) {
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verifyProperties(MF);
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visitMachineFunctionBefore();
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for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
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MFI!=MFE; ++MFI) {
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visitMachineBasicBlockBefore(&*MFI);
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for (const MachineBasicBlock &MBB : MF) {
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visitMachineBasicBlockBefore(&MBB);
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// Keep track of the current bundle header.
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const MachineInstr *CurBundle = nullptr;
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// Do we expect the next instruction to be part of the same bundle?
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bool InBundle = false;
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for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(),
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MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
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if (MBBI->getParent() != &*MFI) {
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report("Bad instruction parent pointer", &*MFI);
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errs() << "Instruction: " << *MBBI;
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for (const MachineInstr &MI : MBB.instrs()) {
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if (MI.getParent() != &MBB) {
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report("Bad instruction parent pointer", &MBB);
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errs() << "Instruction: " << MI;
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continue;
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}
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// Check for consistent bundle flags.
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if (InBundle && !MBBI->isBundledWithPred())
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if (InBundle && !MI.isBundledWithPred())
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report("Missing BundledPred flag, "
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"BundledSucc was set on predecessor",
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&*MBBI);
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if (!InBundle && MBBI->isBundledWithPred())
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&MI);
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if (!InBundle && MI.isBundledWithPred())
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report("BundledPred flag is set, "
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"but BundledSucc not set on predecessor",
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&*MBBI);
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&MI);
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// Is this a bundle header?
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if (!MBBI->isInsideBundle()) {
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if (!MI.isInsideBundle()) {
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if (CurBundle)
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visitMachineBundleAfter(CurBundle);
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CurBundle = &*MBBI;
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CurBundle = &MI;
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visitMachineBundleBefore(CurBundle);
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} else if (!CurBundle)
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report("No bundle header", &*MBBI);
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visitMachineInstrBefore(&*MBBI);
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for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
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const MachineInstr &MI = *MBBI;
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report("No bundle header", &MI);
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visitMachineInstrBefore(&MI);
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for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
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const MachineOperand &Op = MI.getOperand(I);
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if (Op.getParent() != &MI) {
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// Make sure to use correct addOperand / RemoveOperand / ChangeTo
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@ -426,16 +417,16 @@ unsigned MachineVerifier::verify(MachineFunction &MF) {
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visitMachineOperand(&Op, I);
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}
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visitMachineInstrAfter(&*MBBI);
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visitMachineInstrAfter(&MI);
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// Was this the last bundled instruction?
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InBundle = MBBI->isBundledWithSucc();
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InBundle = MI.isBundledWithSucc();
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}
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if (CurBundle)
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visitMachineBundleAfter(CurBundle);
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if (InBundle)
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report("BundledSucc flag set on last instruction in block", &MFI->back());
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visitMachineBasicBlockAfter(&*MFI);
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report("BundledSucc flag set on last instruction in block", &MBB.back());
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visitMachineBasicBlockAfter(&MBB);
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}
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visitMachineFunctionAfter();
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@ -546,9 +537,8 @@ void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
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BBInfo &MInfo = MBBInfoMap[MBB];
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if (!MInfo.reachable) {
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MInfo.reachable = true;
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for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
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SuE = MBB->succ_end(); SuI != SuE; ++SuI)
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markReachable(*SuI);
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for (const MachineBasicBlock *Succ : MBB->successors())
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markReachable(Succ);
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}
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}
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@ -640,14 +630,13 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
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}
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// Check the predecessor list.
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for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
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E = MBB->pred_end(); I != E; ++I) {
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if (!FunctionBlocks.count(*I))
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for (const MachineBasicBlock *Pred : MBB->predecessors()) {
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if (!FunctionBlocks.count(Pred))
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report("MBB has predecessor that isn't part of the function.", MBB);
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if (!MBBInfoMap[*I].Succs.count(MBB)) {
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if (!MBBInfoMap[Pred].Succs.count(MBB)) {
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report("Inconsistent CFG", MBB);
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errs() << "MBB is not in the successor list of the predecessor "
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<< printMBBReference(*(*I)) << ".\n";
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<< printMBBReference(*Pred) << ".\n";
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}
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}
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@ -670,8 +659,7 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
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// check whether its answers match up with reality.
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if (!TBB && !FBB) {
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// Block falls through to its successor.
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MachineFunction::const_iterator MBBI = MBB->getIterator();
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++MBBI;
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MachineFunction::const_iterator MBBI = std::next(MBB->getIterator());
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if (MBBI == MF->end()) {
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// It's possible that the block legitimately ends with a noreturn
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// call or an unreachable, in which case it won't actually fall
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@ -728,8 +716,7 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
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}
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} else if (TBB && !FBB && !Cond.empty()) {
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// Block conditionally branches somewhere, otherwise falls through.
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MachineFunction::const_iterator MBBI = MBB->getIterator();
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++MBBI;
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MachineFunction::const_iterator MBBI = std::next(MBB->getIterator());
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if (MBBI == MF->end()) {
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report("MBB conditionally falls through out of function!", MBB);
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} else if (MBB->succ_size() == 1) {
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@ -1485,12 +1472,10 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
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verifyInlineAsm(MI);
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// Check the MachineMemOperands for basic consistency.
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for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
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E = MI->memoperands_end();
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I != E; ++I) {
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if ((*I)->isLoad() && !MI->mayLoad())
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for (MachineMemOperand *Op : MI->memoperands()) {
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if (Op->isLoad() && !MI->mayLoad())
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report("Missing mayLoad flag", MI);
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if ((*I)->isStore() && !MI->mayStore())
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if (Op->isStore() && !MI->mayStore())
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report("Missing mayStore flag", MI);
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}
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@ -2101,10 +2086,10 @@ void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
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// Kill any masked registers.
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while (!regMasks.empty()) {
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const uint32_t *Mask = regMasks.pop_back_val();
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for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I)
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if (Register::isPhysicalRegister(*I) &&
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MachineOperand::clobbersPhysReg(Mask, *I))
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regsDead.push_back(*I);
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for (unsigned Reg : regsLive)
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if (Register::isPhysicalRegister(Reg) &&
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MachineOperand::clobbersPhysReg(Mask, Reg))
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regsDead.push_back(Reg);
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}
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set_subtract(regsLive, regsDead); regsDead.clear();
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set_union(regsLive, regsDefined); regsDefined.clear();
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@ -2301,11 +2286,10 @@ void MachineVerifier::calcRegsRequired() {
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SmallPtrSet<const MachineBasicBlock*, 8> todo;
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for (const auto &MBB : *MF) {
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BBInfo &MInfo = MBBInfoMap[&MBB];
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for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
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PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
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BBInfo &PInfo = MBBInfoMap[*PrI];
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for (const MachineBasicBlock *Pred : MBB.predecessors()) {
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BBInfo &PInfo = MBBInfoMap[Pred];
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if (PInfo.addRequired(MInfo.vregsLiveIn))
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todo.insert(*PrI);
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todo.insert(Pred);
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}
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}
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@ -2315,13 +2299,12 @@ void MachineVerifier::calcRegsRequired() {
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const MachineBasicBlock *MBB = *todo.begin();
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todo.erase(MBB);
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BBInfo &MInfo = MBBInfoMap[MBB];
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for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
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PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
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if (*PrI == MBB)
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for (const MachineBasicBlock *Pred : MBB->predecessors()) {
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if (Pred == MBB)
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continue;
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BBInfo &SInfo = MBBInfoMap[*PrI];
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BBInfo &SInfo = MBBInfoMap[Pred];
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if (SInfo.addRequired(MInfo.vregsRequired))
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todo.insert(*PrI);
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todo.insert(Pred);
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}
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}
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}
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@ -2405,23 +2388,19 @@ void MachineVerifier::visitMachineFunctionAfter() {
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// Check for killed virtual registers that should be live out.
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for (const auto &MBB : *MF) {
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BBInfo &MInfo = MBBInfoMap[&MBB];
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for (RegSet::iterator
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I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
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++I)
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if (MInfo.regsKilled.count(*I)) {
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for (unsigned VReg : MInfo.vregsRequired)
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if (MInfo.regsKilled.count(VReg)) {
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report("Virtual register killed in block, but needed live out.", &MBB);
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errs() << "Virtual register " << printReg(*I)
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errs() << "Virtual register " << printReg(VReg)
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<< " is used after the block.\n";
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}
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}
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if (!MF->empty()) {
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BBInfo &MInfo = MBBInfoMap[&MF->front()];
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for (RegSet::iterator
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I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
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++I) {
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for (unsigned VReg : MInfo.vregsRequired) {
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report("Virtual register defs don't dominate all uses.", MF);
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report_context_vreg(*I);
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report_context_vreg(VReg);
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}
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}
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@ -2783,9 +2762,8 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
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VNI->def == LiveInts->getMBBStartIdx(&*MFI);
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// Check that VNI is live-out of all predecessors.
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for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
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PE = MFI->pred_end(); PI != PE; ++PI) {
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SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
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for (const MachineBasicBlock *Pred : MFI->predecessors()) {
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SlotIndex PEnd = LiveInts->getMBBEndIdx(Pred);
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const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
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// All predecessors must have a live-out value. However for a phi
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@ -2793,9 +2771,9 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
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// only one of the subregisters (not necessarily the current one) needs to
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// be defined.
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if (!PVNI && (LaneMask.none() || !IsPHI)) {
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if (LiveRangeCalc::isJointlyDominated(*PI, Undefs, *Indexes))
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if (LiveRangeCalc::isJointlyDominated(Pred, Undefs, *Indexes))
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continue;
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report("Register not marked live out of predecessor", *PI);
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report("Register not marked live out of predecessor", Pred);
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report_context(LR, Reg, LaneMask);
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report_context(*VNI);
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errs() << " live into " << printMBBReference(*MFI) << '@'
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@ -2806,10 +2784,10 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
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// Only PHI-defs can take different predecessor values.
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if (!IsPHI && PVNI != VNI) {
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report("Different value live out of predecessor", *PI);
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report("Different value live out of predecessor", Pred);
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report_context(LR, Reg, LaneMask);
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errs() << "Valno #" << PVNI->id << " live out of "
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<< printMBBReference(*(*PI)) << '@' << PEnd << "\nValno #"
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<< printMBBReference(*Pred) << '@' << PEnd << "\nValno #"
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<< VNI->id << " live into " << printMBBReference(*MFI) << '@'
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<< LiveInts->getMBBStartIdx(&*MFI) << '\n';
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}
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@ -2865,10 +2843,9 @@ void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
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report_context(LI);
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for (unsigned comp = 0; comp != NumComp; ++comp) {
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errs() << comp << ": valnos";
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for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
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E = LI.vni_end(); I!=E; ++I)
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if (comp == ConEQ.getEqClass(*I))
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errs() << ' ' << (*I)->id;
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for (const VNInfo *I : LI.valnos)
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if (comp == ConEQ.getEqClass(I))
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errs() << ' ' << I->id;
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errs() << '\n';
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}
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}
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@ -2955,15 +2932,14 @@ void MachineVerifier::verifyStackFrame() {
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// Make sure the exit state of any predecessor is consistent with the entry
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// state.
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for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
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E = MBB->pred_end(); I != E; ++I) {
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if (Reachable.count(*I) &&
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(SPState[(*I)->getNumber()].ExitValue != BBState.EntryValue ||
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SPState[(*I)->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
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for (const MachineBasicBlock *Pred : MBB->predecessors()) {
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if (Reachable.count(Pred) &&
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(SPState[Pred->getNumber()].ExitValue != BBState.EntryValue ||
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SPState[Pred->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
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report("The exit stack state of a predecessor is inconsistent.", MBB);
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errs() << "Predecessor " << printMBBReference(*(*I))
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<< " has exit state (" << SPState[(*I)->getNumber()].ExitValue
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<< ", " << SPState[(*I)->getNumber()].ExitIsSetup << "), while "
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errs() << "Predecessor " << printMBBReference(*Pred)
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<< " has exit state (" << SPState[Pred->getNumber()].ExitValue
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<< ", " << SPState[Pred->getNumber()].ExitIsSetup << "), while "
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<< printMBBReference(*MBB) << " has entry state ("
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<< BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
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}
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@ -2971,15 +2947,14 @@ void MachineVerifier::verifyStackFrame() {
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// Make sure the entry state of any successor is consistent with the exit
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// state.
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for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
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E = MBB->succ_end(); I != E; ++I) {
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if (Reachable.count(*I) &&
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(SPState[(*I)->getNumber()].EntryValue != BBState.ExitValue ||
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SPState[(*I)->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
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for (const MachineBasicBlock *Succ : MBB->successors()) {
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if (Reachable.count(Succ) &&
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(SPState[Succ->getNumber()].EntryValue != BBState.ExitValue ||
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SPState[Succ->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
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report("The entry stack state of a successor is inconsistent.", MBB);
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errs() << "Successor " << printMBBReference(*(*I))
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<< " has entry state (" << SPState[(*I)->getNumber()].EntryValue
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<< ", " << SPState[(*I)->getNumber()].EntryIsSetup << "), while "
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errs() << "Successor " << printMBBReference(*Succ)
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<< " has entry state (" << SPState[Succ->getNumber()].EntryValue
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<< ", " << SPState[Succ->getNumber()].EntryIsSetup << "), while "
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<< printMBBReference(*MBB) << " has exit state ("
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<< BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
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}
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