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We'd still like to register allocate r2 on darwin before the callee-save

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regs.

llvm-svn: 33635
This commit is contained in:
Nate Begeman 2007-01-29 22:57:48 +00:00
parent 5fdc488d4a
commit 32cbf413b6
1 changed files with 6 additions and 6 deletions
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12
lib/Target/PowerPC/PPCRegisterInfo.td
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@ -209,9 +209,9 @@ def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<107>;
// Allocate volatiles first
// then nonvolatiles in reverse order since stmw/lmw save from rN to r31
def GPRC : RegisterClass<"PPC", [i32], 32,
[R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
[R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
R16, R15, R14, R2, R13, R31, R0, R1, LR]>
R16, R15, R14, R13, R31, R0, R1, LR]>
{
let MethodProtos = [{
iterator allocation_order_begin(const MachineFunction &MF) const;
@ -220,14 +220,14 @@ def GPRC : RegisterClass<"PPC", [i32], 32,
let MethodBodies = [{
GPRCClass::iterator
GPRCClass::allocation_order_begin(const MachineFunction &MF) const {
// In Linux, r2 is reserved for the OS.
if (!MF.getTarget().getSubtarget<PPCSubtarget>().isDarwin())
return begin()+1;
return begin();
}
GPRCClass::iterator
GPRCClass::allocation_order_end(const MachineFunction &MF) const {
// In Linux, r2 is reserved for the OS.
if (!MF.getTarget().getSubtarget<PPCSubtarget>().isDarwin())
return end()-6;
// On PPC64, r13 is the thread pointer. Never allocate this register.
// Note that this is overconservative, as it also prevents allocation of
// R31 when the FP is not needed.