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Add more ARM instruction encodings for 's' bit set and "rs" register encoding
bits. Patch by Johnny Chen. llvm-svn: 85167
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@ -398,6 +398,7 @@ multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
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def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
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IIC_iALUi, opc, "s $dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
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let Inst{20} = 1;
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let Inst{25} = 1;
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}
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def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
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@ -405,6 +406,7 @@ multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
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[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
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let isCommutable = Commutable;
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let Inst{4} = 0;
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let Inst{20} = 1;
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let Inst{25} = 0;
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}
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def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
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@ -412,6 +414,7 @@ multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
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[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
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let Inst{4} = 1;
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let Inst{7} = 0;
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let Inst{20} = 1;
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let Inst{25} = 0;
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}
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}
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@ -512,6 +515,7 @@ multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
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[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
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Requires<[IsARM, CarryDefIsUsed]> {
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let Defs = [CPSR];
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let Inst{20} = 1;
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let Inst{25} = 1;
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}
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def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
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@ -520,6 +524,7 @@ multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
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Requires<[IsARM, CarryDefIsUsed]> {
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let Defs = [CPSR];
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let Inst{4} = 0;
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let Inst{20} = 1;
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let Inst{25} = 0;
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}
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def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
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@ -529,6 +534,7 @@ multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
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let Defs = [CPSR];
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let Inst{4} = 1;
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let Inst{7} = 0;
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let Inst{20} = 1;
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let Inst{25} = 0;
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}
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}
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@ -1091,18 +1097,28 @@ def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
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def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
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IIC_iALUsr, "rsb", " $dst, $a, $b",
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[(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
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[(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> {
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let Inst{4} = 1;
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let Inst{7} = 0;
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let Inst{25} = 0;
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}
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// RSB with 's' bit set.
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let Defs = [CPSR] in {
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def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
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IIC_iALUi, "rsb", "s $dst, $a, $b",
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[(set GPR:$dst, (subc so_imm:$b, GPR:$a))]> {
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let Inst{20} = 1;
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let Inst{25} = 1;
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}
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def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
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IIC_iALUsr, "rsb", "s $dst, $a, $b",
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[(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
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[(set GPR:$dst, (subc so_reg:$b, GPR:$a))]> {
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let Inst{4} = 1;
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let Inst{7} = 0;
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let Inst{20} = 1;
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let Inst{25} = 0;
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}
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}
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let Uses = [CPSR] in {
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