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[Hexagon] Add patterns for compares of i1 values
llvm-svn: 326220
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@ -679,8 +679,10 @@ def: Pat<(i32 (zext (i1 (seteq I32:$Rs, anyimm:$s8)))),
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def: Pat<(i32 (zext (i1 (setne I32:$Rs, anyimm:$s8)))),
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(A4_rcmpneqi I32:$Rs, imm:$s8)>;
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def: Pat<(i1 (setne I1:$Ps, I1:$Pt)),
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(C2_xor I1:$Ps, I1:$Pt)>;
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def: Pat<(i1 (seteq I1:$Ps, (i1 -1))), (I1:$Ps)>;
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def: Pat<(i1 (setne I1:$Ps, (i1 -1))), (C2_not I1:$Ps)>;
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def: Pat<(i1 (seteq I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, (C2_not I1:$Pt))>;
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def: Pat<(i1 (setne I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, I1:$Pt)>;
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def: Pat<(i1 (seteq V4I8:$Rs, V4I8:$Rt)),
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(A2_vcmpbeq (ToZext64 $Rs), (ToZext64 $Rt))>;
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27
test/CodeGen/Hexagon/isel-setcc-i1.ll
Normal file
27
test/CodeGen/Hexagon/isel-setcc-i1.ll
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@ -0,0 +1,27 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; Check that this compiles successfully.
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; CHECK: if (p0)
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target triple = "hexagon"
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define void @fred() #0 {
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b0:
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br label %b1
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b1: ; preds = %b1, %b0
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%v2 = load i32, i32* undef, align 4
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%v3 = select i1 undef, i32 %v2, i32 0
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%v4 = and i32 %v3, 7
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%v5 = icmp eq i32 %v4, 4
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%v6 = or i1 undef, %v5
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%v7 = and i1 undef, %v6
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%v8 = xor i1 %v7, true
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%v9 = or i1 undef, %v8
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br i1 %v9, label %b10, label %b1
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b10: ; preds = %b1
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unreachable
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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