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Rename mattr names for AVX-512 to from avx-512 -> avx512f, avx-512-pfi -> av512pf, avx-512-cdi -> avx512cd, avx-512-eri->avx512er. This matches better with official docs and what gcc patches appearto be using. I didn't touch the has* functions or the feature flag names to avoid change the td and lowering file while commits are still happening.
llvm-svn: 188859
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@ -86,16 +86,16 @@ def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",
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def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
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def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
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"Enable AVX2 instructions",
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"Enable AVX2 instructions",
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[FeatureAVX]>;
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[FeatureAVX]>;
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def FeatureAVX512 : SubtargetFeature<"avx-512", "X86SSELevel", "AVX512",
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def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
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"Enable AVX-512 instructions",
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"Enable AVX-512 instructions",
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[FeatureAVX2]>;
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[FeatureAVX2]>;
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def FeatureERI : SubtargetFeature<"avx-512-eri", "HasERI", "true",
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def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true",
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"Enable AVX-512 Exponential and Reciprocal Instructions",
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"Enable AVX-512 Exponential and Reciprocal Instructions",
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[FeatureAVX512]>;
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[FeatureAVX512]>;
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def FeatureCDI : SubtargetFeature<"avx-512-cdi", "HasCDI", "true",
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def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true",
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"Enable AVX-512 Conflict Detection Instructions",
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"Enable AVX-512 Conflict Detection Instructions",
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[FeatureAVX512]>;
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[FeatureAVX512]>;
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def FeaturePFI : SubtargetFeature<"avx-512-pfi", "HasPFI", "true",
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def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true",
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"Enable AVX-512 PreFetch Instructions",
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"Enable AVX-512 PreFetch Instructions",
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[FeatureAVX512]>;
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[FeatureAVX512]>;
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@ -352,7 +352,7 @@ void X86Subtarget::AutoDetectSubtargetFeatures() {
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ToggleFeature(X86::FeatureRTM);
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ToggleFeature(X86::FeatureRTM);
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}
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}
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if (IsIntel && ((EBX >> 16) & 0x1)) {
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if (IsIntel && ((EBX >> 16) & 0x1)) {
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X86SSELevel = AVX512;
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X86SSELevel = AVX512F;
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ToggleFeature(X86::FeatureAVX512);
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ToggleFeature(X86::FeatureAVX512);
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}
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}
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if (IsIntel && ((EBX >> 18) & 0x1)) {
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if (IsIntel && ((EBX >> 18) & 0x1)) {
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@ -42,7 +42,7 @@ enum Style {
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class X86Subtarget : public X86GenSubtargetInfo {
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class X86Subtarget : public X86GenSubtargetInfo {
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protected:
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protected:
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enum X86SSEEnum {
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enum X86SSEEnum {
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NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512
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NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
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};
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};
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enum X863DNowEnum {
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enum X863DNowEnum {
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@ -258,7 +258,7 @@ public:
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bool hasSSE42() const { return X86SSELevel >= SSE42; }
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bool hasSSE42() const { return X86SSELevel >= SSE42; }
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bool hasAVX() const { return X86SSELevel >= AVX; }
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bool hasAVX() const { return X86SSELevel >= AVX; }
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bool hasAVX2() const { return X86SSELevel >= AVX2; }
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bool hasAVX2() const { return X86SSELevel >= AVX2; }
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bool hasAVX512() const { return X86SSELevel >= AVX512; }
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bool hasAVX512() const { return X86SSELevel >= AVX512F; }
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bool hasFp256() const { return hasAVX(); }
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bool hasFp256() const { return hasAVX(); }
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bool hasInt256() const { return hasAVX2(); }
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bool hasInt256() const { return hasAVX2(); }
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bool hasSSE4A() const { return HasSSE4A; }
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bool hasSSE4A() const { return HasSSE4A; }
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