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Remove the TII::scheduleTwoAddrSource() hook.
It never does anything when running 'make check', and it get's in the way of updating live intervals in 2-addr. The hook was originally added to help form IT blocks in Thumb2 code before register allocation, but the pass ordering has changed since then, and we run if-conversion after register allocation now. When the MI scheduler is enabled, there will be no less than two schedulers between 2-addr and Thumb2ITBlockPass, so this hook is unlikely to help anything. llvm-svn: 161794
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@ -188,14 +188,6 @@ public:
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const MachineInstr *Orig,
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const MachineInstr *Orig,
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const TargetRegisterInfo &TRI) const = 0;
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const TargetRegisterInfo &TRI) const = 0;
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/// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
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/// two-addrss instruction inserted by two-address pass.
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virtual void scheduleTwoAddrSource(MachineInstr *SrcMI,
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MachineInstr *UseMI,
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const TargetRegisterInfo &TRI) const {
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// Do nothing.
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}
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/// duplicate - Create a duplicate of the Orig instruction in MF. This is like
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/// duplicate - Create a duplicate of the Orig instruction in MF. This is like
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/// MachineFunction::CloneMachineInstr(), but the target may update operands
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/// MachineFunction::CloneMachineInstr(), but the target may update operands
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/// that are required to be unique.
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/// that are required to be unique.
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@ -1352,17 +1352,6 @@ TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI,
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}
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}
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}
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}
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}
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}
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// We didn't change anything if there was a single tied pair, and that
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// pair didn't require copies.
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if (AllUsesCopied || TiedPairs.size() > 1) {
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// Schedule the source copy / remat inserted to form two-address
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// instruction. FIXME: Does it matter the distance map may not be
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// accurate after it's scheduled?
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MachineBasicBlock::iterator PrevMI = MI;
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--PrevMI;
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TII->scheduleTwoAddrSource(PrevMI, MI, *TRI);
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}
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}
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}
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/// runOnMachineFunction - Reduce two-address instructions to two operands.
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/// runOnMachineFunction - Reduce two-address instructions to two operands.
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@ -563,48 +563,6 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
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return Offset == 0;
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return Offset == 0;
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}
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}
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/// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
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/// two-addrss instruction inserted by two-address pass.
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void
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Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI,
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MachineInstr *UseMI,
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const TargetRegisterInfo &TRI) const {
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if (SrcMI->getOpcode() != ARM::tMOVr || SrcMI->getOperand(1).isKill())
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return;
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unsigned PredReg = 0;
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ARMCC::CondCodes CC = getInstrPredicate(UseMI, PredReg);
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if (CC == ARMCC::AL || PredReg != ARM::CPSR)
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return;
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// Schedule the copy so it doesn't come between previous instructions
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// and UseMI which can form an IT block.
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unsigned SrcReg = SrcMI->getOperand(1).getReg();
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ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
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MachineBasicBlock *MBB = UseMI->getParent();
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MachineBasicBlock::iterator MBBI = SrcMI;
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unsigned NumInsts = 0;
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while (--MBBI != MBB->begin()) {
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if (MBBI->isDebugValue())
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continue;
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MachineInstr *NMI = &*MBBI;
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ARMCC::CondCodes NCC = getInstrPredicate(NMI, PredReg);
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if (!(NCC == CC || NCC == OCC) ||
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NMI->modifiesRegister(SrcReg, &TRI) ||
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NMI->modifiesRegister(ARM::CPSR, &TRI))
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break;
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if (++NumInsts == 4)
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// Too many in a row!
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return;
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}
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if (NumInsts) {
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MBB->remove(SrcMI);
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MBB->insert(++MBBI, SrcMI);
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}
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}
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ARMCC::CondCodes
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ARMCC::CondCodes
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llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
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llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
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unsigned Opc = MI->getOpcode();
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unsigned Opc = MI->getOpcode();
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@ -57,11 +57,6 @@ public:
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const TargetRegisterClass *RC,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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const TargetRegisterInfo *TRI) const;
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/// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
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/// two-addrss instruction inserted by two-address pass.
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void scheduleTwoAddrSource(MachineInstr *SrcMI, MachineInstr *UseMI,
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const TargetRegisterInfo &TRI) const;
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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/// always be able to get register info as well (through this method).
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