mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-01-26 22:34:39 +00:00
massive DAGISel patch. lots and lots more stuff compiles now
llvm-svn: 24483
This commit is contained in:
Andrew Lenharth
parent
d2f6fcf327
commit
33e8022557
@ -117,7 +117,9 @@ void AlphaCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
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case Alpha::ALTENT:
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case Alpha::PCLABEL:
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case Alpha::MEMLABEL:
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case Alpha::IDEF:
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case Alpha::IDEF_I:
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case Alpha::IDEF_F32:
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case Alpha::IDEF_F64:
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break; //skip these
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}
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}
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@ -38,6 +38,10 @@ namespace {
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class AlphaDAGToDAGISel : public SelectionDAGISel {
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AlphaTargetLowering AlphaLowering;
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static const int IMM_LOW = -32768;
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static const int IMM_HIGH = 32767;
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static const int IMM_MULT = 65536;
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public:
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AlphaDAGToDAGISel(TargetMachine &TM)
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: SelectionDAGISel(AlphaLowering), AlphaLowering(TM) {}
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@ -108,13 +112,42 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
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case ISD::TAILCALL:
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case ISD::CALL: return SelectCALL(Op);
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case ISD::DYNAMIC_STACKALLOC:
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assert(0 && "You want these too?");
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case ISD::DYNAMIC_STACKALLOC: {
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if (!isa<ConstantSDNode>(N->getOperand(2)) ||
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cast<ConstantSDNode>(N->getOperand(2))->getValue() != 0) {
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std::cerr << "Cannot allocate stack object with greater alignment than"
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<< " the stack alignment yet!";
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abort();
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}
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SDOperand Chain = Select(N->getOperand(0));
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SDOperand Amt = Select(N->getOperand(1));
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SDOperand Reg = CurDAG->getRegister(Alpha::R30, MVT::i64);
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SDOperand Val = CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64);
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Chain = Val.getValue(1);
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// Subtract the amount (guaranteed to be a multiple of the stack alignment)
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// from the stack pointer, giving us the result pointer.
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SDOperand Result = CurDAG->getTargetNode(Alpha::SUBQ, MVT::i64, Val, Amt);
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// Copy this result back into R30.
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Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, Reg, Result);
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// Copy this result back out of R30 to make sure we're not using the stack
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// space without decrementing the stack pointer.
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Result = CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64);
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// Finally, replace the DYNAMIC_STACKALLOC with the copyfromreg.
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CodeGenMap[Op.getValue(0)] = Result;
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CodeGenMap[Op.getValue(1)] = Result.getValue(1);
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return SDOperand(Result.Val, Op.ResNo);
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}
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case ISD::BRCOND: {
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SDOperand Chain = Select(N->getOperand(0));
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SDOperand CC = Select(N->getOperand(1));
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CurDAG->SelectNodeTo(N, Alpha::BNE, MVT::Other, CC, Chain);
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MachineBasicBlock *Dest =
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cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
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CurDAG->SelectNodeTo(N, Alpha::BNE, MVT::Other, CC, CurDAG->getBasicBlock(Dest), Chain);
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return SDOperand(N, 0);
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}
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case ISD::LOAD:
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@ -148,6 +181,33 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
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getI64Imm(0), Address, Chain);
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return SDOperand(N, Op.ResNo);
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}
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case ISD::STORE:
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case ISD::TRUNCSTORE: {
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SDOperand Chain = Select(N->getOperand(0));
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SDOperand Value = Select(N->getOperand(1));
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SDOperand Address = Select(N->getOperand(2));
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unsigned Opc = Alpha::WTF;
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if (N->getOpcode() == ISD::STORE) {
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switch (N->getOperand(1).getValueType()) {
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case MVT::i64: Opc = Alpha::STQ; break;
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case MVT::f64: Opc = Alpha::STT; break;
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case MVT::f32: Opc = Alpha::STS; break;
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default: assert(0 && "Bad store!");
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};
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} else { //TRUNCSTORE
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switch (cast<VTSDNode>(N->getOperand(4))->getVT()) {
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case MVT::i32: Opc = Alpha::STL; break;
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case MVT::i16: Opc = Alpha::STW; break;
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case MVT::i8: Opc = Alpha::STB; break;
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default: assert(0 && "Bad truncstore!");
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};
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}
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CurDAG->SelectNodeTo(N, Opc, MVT::Other, Value, getI64Imm(0), Address,
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Chain);
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return SDOperand(N, 0);
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}
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case ISD::BR: {
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CurDAG->SelectNodeTo(N, Alpha::BR_DAG, MVT::Other, N->getOperand(1),
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@ -155,32 +215,19 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
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return SDOperand(N, 0);
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}
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case ISD::UNDEF:
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if (N->getValueType(0) == MVT::i64)
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CurDAG->SelectNodeTo(N, Alpha::IDEF, MVT::i64);
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// else if (N->getValueType(0) == MVT::f32)
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// CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_F4, MVT::f32);
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// else
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// CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_F8, MVT::f64);
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return SDOperand(N, 0);
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case ISD::FrameIndex: {
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// int FI = cast<FrameIndexSDNode>(N)->getIndex();
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// CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
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// CurDAG->getTargetFrameIndex(FI, MVT::i32),
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// getI32Imm(0));
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// return SDOperand(N, 0);
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assert(0 && "Frame?, you are suppose to look through the window, not at the frame!");
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int FI = cast<FrameIndexSDNode>(N)->getIndex();
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CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
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CurDAG->getTargetFrameIndex(FI, MVT::i32),
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getI64Imm(0));
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return SDOperand(N, 0);
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}
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case ISD::ConstantPool: {
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// Constant *C = cast<ConstantPoolSDNode>(N)->get();
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// SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i32);
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// if (PICEnabled)
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// Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),CPI);
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// else
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// Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, CPI);
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// CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, CPI);
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// return SDOperand(N, 0);
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assert(0 && "Constants are overrated");
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Constant *C = cast<ConstantPoolSDNode>(N)->get();
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SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
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Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, getGlobalBaseReg());
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CurDAG->SelectNodeTo(N, Alpha::LDAr, MVT::i64, CPI, Tmp);
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return SDOperand(N, 0);
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}
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case ISD::GlobalAddress: {
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GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
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@ -219,15 +266,45 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
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CurDAG->SelectNodeTo(N, Alpha::RETDAG, MVT::Other, Chain);
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return SDOperand(N, 0);
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}
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case ISD::Constant: {
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int64_t val = (int64_t)cast<ConstantSDNode>(N)->getValue();
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if (val > (int64_t)IMM_HIGH +(int64_t)IMM_HIGH* (int64_t)IMM_MULT ||
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val < (int64_t)IMM_LOW + (int64_t)IMM_LOW * (int64_t)IMM_MULT) {
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MachineConstantPool *CP = BB->getParent()->getConstantPool();
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ConstantUInt *C =
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ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , val);
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SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
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Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, getGlobalBaseReg());
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CurDAG->SelectNodeTo(N, Alpha::LDAr, MVT::i64, CPI, Tmp);
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return SDOperand(N, 0);
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}
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}
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case ISD::ConstantFP:
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if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N)) {
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bool isDouble = N->getValueType(0) == MVT::f64;
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MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32;
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if (CN->isExactlyValue(+0.0)) {
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CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS, T,
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CurDAG->getRegister(Alpha::F31, T),
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CurDAG->getRegister(Alpha::F31, T));
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return SDOperand(N, 0);
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} else if ( CN->isExactlyValue(-0.0)) {
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CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS, T,
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CurDAG->getRegister(Alpha::F31, T),
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CurDAG->getRegister(Alpha::F31, T));
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return SDOperand(N, 0);
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} else {
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abort();
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}
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}
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}
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return SelectCode(Op);
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}
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SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
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//TODO: add flag stuff to prevent nondeturministic breakage!
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SDNode *N = Op.Val;
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SDOperand Chain = Select(N->getOperand(0));
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SDOperand Addr = Select(N->getOperand(1));
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@ -251,10 +328,12 @@ SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
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for (int i = 0; i < std::min(6, count); ++i) {
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if (MVT::isInteger(TypeOperands[i])) {
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Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i]);
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} else {
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assert(0 && "No FP support yet");
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}
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} else if (TypeOperands[i] == MVT::f64 || TypeOperands[i] == MVT::f64) {
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Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i]);
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} else
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assert(0 && "Unknown operand");
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}
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assert(CallOperands.size() <= 6 && "Too big a call");
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Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr);
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@ -271,6 +350,14 @@ SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
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Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64).getValue(1);
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CallResults.push_back(Chain.getValue(0));
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break;
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case MVT::f32:
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Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32).getValue(1);
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CallResults.push_back(Chain.getValue(0));
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break;
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case MVT::f64:
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Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64).getValue(1);
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CallResults.push_back(Chain.getValue(0));
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break;
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}
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CallResults.push_back(Chain);
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@ -592,7 +592,9 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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return Result;
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}
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case ISD::UNDEF: {
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BuildMI(BB, Alpha::IDEF, 0, Result);
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Opc = isFP ? (DestType == MVT::f32 ? Alpha::IDEF_F32 : Alpha::IDEF_F64)
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: Alpha::IDEF_I;
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BuildMI(BB, Opc, 0, Result);
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return Result;
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}
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@ -1610,7 +1612,13 @@ void AlphaISel::Select(SDOperand N) {
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case ISD::ImplicitDef:
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++count_ins;
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Select(N.getOperand(0));
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BuildMI(BB, Alpha::IDEF, 0,
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switch(N.getValueType()) {
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case MVT::f32: Opc = Alpha::IDEF_F32; break;
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case MVT::f64: Opc = Alpha::IDEF_F64; break;
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case MVT::i64: Opc = Alpha::IDEF_I; break;
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default: assert(0 && "should have been legalized");
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};
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BuildMI(BB, Opc, 0,
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cast<RegisterSDNode>(N.getOperand(1))->getReg());
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return;
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@ -218,5 +218,7 @@ class PALForm<bits<6> opcode, dag OL, string asmstr> : InstAlpha<opcode, OL, asm
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// Pseudo instructions.
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class PseudoInstAlpha<dag OL, string nm> : InstAlpha<0, OL, nm> {
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class PseudoInstAlpha<dag OL, string nm, list<dag> pattern> : InstAlpha<0, OL, nm> {
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let Pattern = pattern;
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}
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@ -74,15 +74,22 @@ def sub8 : PatFrag<(ops node:$op1, node:$op2),
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// //#define GP $29
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// //#define SP $30
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def PHI : PseudoInstAlpha<(ops variable_ops), "#phi">;
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def IDEF : PseudoInstAlpha<(ops GPRC:$RA), "#idef $RA">;
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def WTF : PseudoInstAlpha<(ops variable_ops), "#wtf">;
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def ADJUSTSTACKUP : PseudoInstAlpha<(ops variable_ops), "ADJUP">;
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def ADJUSTSTACKDOWN : PseudoInstAlpha<(ops variable_ops), "ADJDOWN">;
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def ALTENT : PseudoInstAlpha<(ops s64imm:$TARGET), "$TARGET:\n">;
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def PCLABEL : PseudoInstAlpha<(ops s64imm:$num), "PCMARKER_$num:\n">;
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def PHI : PseudoInstAlpha<(ops variable_ops), "#phi", []>;
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def IDEF_I : PseudoInstAlpha<(ops GPRC:$RA), "#idef $RA",
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[(set GPRC:$RA, (undef))]>;
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def IDEF_F32 : PseudoInstAlpha<(ops F4RC:$RA), "#idef $RA",
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[(set F4RC:$RA, (undef))]>;
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def IDEF_F64 : PseudoInstAlpha<(ops F8RC:$RA), "#idef $RA",
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[(set F8RC:$RA, (undef))]>;
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def WTF : PseudoInstAlpha<(ops variable_ops), "#wtf", []>;
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def ADJUSTSTACKUP : PseudoInstAlpha<(ops variable_ops), "ADJUP", []>;
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def ADJUSTSTACKDOWN : PseudoInstAlpha<(ops variable_ops), "ADJDOWN", []>;
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def ALTENT : PseudoInstAlpha<(ops s64imm:$TARGET), "$TARGET:\n", []>;
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def PCLABEL : PseudoInstAlpha<(ops s64imm:$num), "PCMARKER_$num:\n",[]>;
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def MEMLABEL : PseudoInstAlpha<(ops s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m),
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"LSMARKER$$$i$$$j$$$k$$$m:\n">;
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"LSMARKER$$$i$$$j$$$k$$$m:\n",[]>;
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//*****************
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//These are shortcuts, the assembler expands them
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@ -97,19 +104,19 @@ def MEMLABEL : PseudoInstAlpha<(ops s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m),
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let isTwoAddress = 1 in {
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//Conditional move of an int based on a FP CC
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def CMOVEQ_FP : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, GPRC:$RSRC_T, F8RC:$RCOND),
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"fbne $RCOND, 42f\n\tbis $RSRC_T,$RSRC_T,$RDEST\n42:\n">;
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"fbne $RCOND, 42f\n\tbis $RSRC_T,$RSRC_T,$RDEST\n42:\n", []>;
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def CMOVEQi_FP : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, u8imm:$L, F8RC:$RCOND),
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"fbne $RCOND, 42f\n\taddq $$31,$L,$RDEST\n42:\n">;
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"fbne $RCOND, 42f\n\taddq $$31,$L,$RDEST\n42:\n", []>;
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def CMOVNE_FP : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, GPRC:$RSRC_T, F8RC:$RCOND),
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"fbeq $RCOND, 42f\n\tbis $RSRC_T,$RSRC_T,$RDEST\n42:\n">;
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"fbeq $RCOND, 42f\n\tbis $RSRC_T,$RSRC_T,$RDEST\n42:\n", []>;
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def CMOVNEi_FP : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, u8imm:$L, F8RC:$RCOND),
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"fbeq $RCOND, 42f\n\taddq $$31,$L,$RDEST\n42:\n">;
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"fbeq $RCOND, 42f\n\taddq $$31,$L,$RDEST\n42:\n", []>;
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//Conditional move of an FP based on a Int CC
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def FCMOVEQ_INT : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, GPRC:$RSRC_T, F8RC:$RCOND),
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"bne $RCOND, 42f\n\tcpys $RSRC_T,$RSRC_T,$RDEST\n42:\n">;
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"bne $RCOND, 42f\n\tcpys $RSRC_T,$RSRC_T,$RDEST\n42:\n", []>;
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def FCMOVNE_INT : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, GPRC:$RSRC_T, F8RC:$RCOND),
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"beq $RCOND, 42f\n\tcpys $RSRC_T,$RSRC_T,$RDEST\n42:\n">;
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"beq $RCOND, 42f\n\tcpys $RSRC_T,$RSRC_T,$RDEST\n42:\n", []>;
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}
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//***********************
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@ -330,9 +337,9 @@ def CMPULE : OForm< 0x10, 0x3D, "cmpule $RA,$RB,$RC",
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def CMPULEi : OFormL<0x10, 0x3D, "cmpule $RA,$L,$RC",
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[(set GPRC:$RC, (setule GPRC:$RA, immUExt8:$L))]>;
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def CMPULT : OForm< 0x10, 0x1D, "cmpult $RA,$RB,$RC",
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[(set GPRC:$RC, (setlt GPRC:$RA, GPRC:$RB))]>;
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[(set GPRC:$RC, (setult GPRC:$RA, GPRC:$RB))]>;
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def CMPULTi : OFormL<0x10, 0x1D, "cmpult $RA,$L,$RC",
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[(set GPRC:$RC, (setlt GPRC:$RA, immUExt8:$L))]>;
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[(set GPRC:$RC, (setult GPRC:$RA, immUExt8:$L))]>;
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//Patterns for unsupported int comparisons
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def : Pat<(setueq GPRC:$X, GPRC:$Y), (CMPEQ GPRC:$X, GPRC:$Y)>;
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@ -588,7 +595,56 @@ def CVTTS : FPForm<0x16, 0x7AC, "cvtts/sui $RB,$RC",
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//def AMASKi : OFormL<0x11, 0x61, "AMASK $RA,$L,$RC", []>; //Architecture mask
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//Constant handling
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def immConst2Part : PatLeaf<(imm), [{
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// immZAP predicate - True if the immediate fits is suitable for use in a
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// ZAP instruction
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int64_t val = (int64_t)N->getValue();
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return (val <= (int64_t)IMM_HIGH +(int64_t)IMM_HIGH* (int64_t)IMM_MULT &
|
||||
val >= (int64_t)IMM_LOW + (int64_t)IMM_LOW * (int64_t)IMM_MULT);
|
||||
}]>;
|
||||
|
||||
//TODO: factor this out
|
||||
def LL16 : SDNodeXForm<imm, [{
|
||||
int64_t l = N->getValue();
|
||||
int64_t y = l / IMM_MULT;
|
||||
if (l % IMM_MULT > IMM_HIGH)
|
||||
++y;
|
||||
return getI64Imm(l - y * IMM_MULT);
|
||||
}]>;
|
||||
//TODO: factor this out
|
||||
def LH16 : SDNodeXForm<imm, [{
|
||||
int64_t l = N->getValue();
|
||||
int64_t y = l / IMM_MULT;
|
||||
if (l % IMM_MULT > IMM_HIGH)
|
||||
++y;
|
||||
return getI64Imm(y);
|
||||
}]>;
|
||||
|
||||
def : Pat<(i64 immConst2Part:$imm),
|
||||
(LDA (LL16 immConst2Part:$imm), (LDAH (LH16 immConst2Part:$imm), R31))>;
|
||||
|
||||
def : Pat<(i64 immSExt16:$imm),
|
||||
(LDA immSExt16:$imm, R31)>;
|
||||
|
||||
//TODO: I want to just define these like this!
|
||||
//def : Pat<(i64 0),
|
||||
// (R31)>;
|
||||
//def : Pat<(f64 0.0),
|
||||
// (F31)>;
|
||||
//def : Pat<(f64 -0.0),
|
||||
// (CPYSNT F31, F31)>;
|
||||
//def : Pat<(f32 0.0),
|
||||
// (F31)>;
|
||||
//def : Pat<(f32 -0.0),
|
||||
// (CPYSNS F31, F31)>;
|
||||
|
||||
//Misc Patterns:
|
||||
|
||||
def : Pat<(sext_inreg GPRC:$RB, i32),
|
||||
(ADDLi GPRC:$RB, 0)>;
|
||||
|
||||
def : Pat<(select GPRC:$which, GPRC:$src1, GPRC:$src2),
|
||||
(CMOVEQ GPRC:$src1, GPRC:$src2, GPRC:$which)>; //may be CMOVNE
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user