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[PPC] Set SP after loading data from stack frame, if no red zone is present
Follow-up to r280705: Make sure that the SP is only restored after all data is loaded from the stack frame, if there is no red zone. This completes the fix for https://llvm.org/bugs/show_bug.cgi?id=26519. Differential Revision: https://reviews.llvm.org/D24466 llvm-svn: 282174
This commit is contained in:
Krzysztof Parzyszek
parent
986cc88263
commit
344cd70c0b
@ -926,7 +926,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
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}
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// Have we generated a STUX instruction to claim stack frame? If so,
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// the frame size will be placed in ScratchReg.
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// the negated frame size will be placed in ScratchReg.
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bool HasSTUX = false;
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// This condition must be kept in sync with canUseAsPrologue.
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@ -986,33 +986,88 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
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if (!HasRedZone) {
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assert(!isPPC64 && "A red zone is always available on PPC64");
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if (HasSTUX) {
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// The frame size is in ScratchReg, and the SPReg has been advanced
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// (downwards) by the frame size: SPReg = old SPReg + ScratchReg.
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// Set ScratchReg to the original SPReg: ScratchReg = SPReg - ScratchReg.
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// The negated frame size is in ScratchReg, and the SPReg has been
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// decremented by the frame size: SPReg = old SPReg + ScratchReg.
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// Since FPOffset, PBPOffset, etc. are relative to the beginning of
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// the stack frame (i.e. the old SP), ideally, we would put the old
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// SP into a register and use it as the base for the stores. The
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// problem is that the only available register may be ScratchReg,
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// which could be R0, and R0 cannot be used as a base address.
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// First, set ScratchReg to the old SP. This may need to be modified
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// later.
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BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBF), ScratchReg)
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.addReg(ScratchReg, RegState::Kill)
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.addReg(SPReg);
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// Now that the stack frame has been allocated, save all the necessary
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// registers using ScratchReg as the base address.
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if (HasFP)
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BuildMI(MBB, MBBI, dl, StoreInst)
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.addReg(FPReg)
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.addImm(FPOffset)
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.addReg(ScratchReg);
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if (FI->usesPICBase())
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BuildMI(MBB, MBBI, dl, StoreInst)
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.addReg(PPC::R30)
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.addImm(PBPOffset)
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.addReg(ScratchReg);
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if (HasBP) {
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BuildMI(MBB, MBBI, dl, StoreInst)
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.addReg(BPReg)
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.addImm(BPOffset)
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.addReg(ScratchReg);
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BuildMI(MBB, MBBI, dl, OrInst, BPReg)
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.addReg(ScratchReg, RegState::Kill)
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.addReg(ScratchReg);
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if (ScratchReg == PPC::R0) {
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// R0 cannot be used as a base register, but it can be used as an
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// index in a store-indexed.
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int LastOffset = 0;
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if (HasFP) {
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// R0 += (FPOffset-LastOffset).
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// Need addic, since addi treats R0 as 0.
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BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
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.addReg(ScratchReg)
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.addImm(FPOffset-LastOffset);
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LastOffset = FPOffset;
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// Store FP into *R0.
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
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.addReg(FPReg, RegState::Kill) // Save FP.
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.addReg(PPC::ZERO)
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.addReg(ScratchReg); // This will be the index (R0 is ok here).
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}
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if (FI->usesPICBase()) {
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// R0 += (PBPOffset-LastOffset).
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BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
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.addReg(ScratchReg)
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.addImm(PBPOffset-LastOffset);
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LastOffset = PBPOffset;
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
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.addReg(PPC::R30, RegState::Kill) // Save PIC base pointer.
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.addReg(PPC::ZERO)
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.addReg(ScratchReg); // This will be the index (R0 is ok here).
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}
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if (HasBP) {
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// R0 += (BPOffset-LastOffset).
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BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
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.addReg(ScratchReg)
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.addImm(BPOffset-LastOffset);
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LastOffset = BPOffset;
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
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.addReg(BPReg, RegState::Kill) // Save BP.
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.addReg(PPC::ZERO)
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.addReg(ScratchReg); // This will be the index (R0 is ok here).
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// BP = R0-LastOffset
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BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), BPReg)
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.addReg(ScratchReg, RegState::Kill)
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.addImm(-LastOffset);
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}
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} else {
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// ScratchReg is not R0, so use it as the base register. It is
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// already set to the old SP, so we can use the offsets directly.
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// Now that the stack frame has been allocated, save all the necessary
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// registers using ScratchReg as the base address.
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if (HasFP)
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BuildMI(MBB, MBBI, dl, StoreInst)
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.addReg(FPReg)
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.addImm(FPOffset)
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.addReg(ScratchReg);
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if (FI->usesPICBase())
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BuildMI(MBB, MBBI, dl, StoreInst)
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.addReg(PPC::R30)
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.addImm(PBPOffset)
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.addReg(ScratchReg);
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if (HasBP) {
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BuildMI(MBB, MBBI, dl, StoreInst)
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.addReg(BPReg)
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.addImm(BPOffset)
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.addReg(ScratchReg);
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BuildMI(MBB, MBBI, dl, OrInst, BPReg)
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.addReg(ScratchReg, RegState::Kill)
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.addReg(ScratchReg);
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}
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}
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} else {
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// The frame size is a known 16-bit constant (fitting in the immediate
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@ -1190,6 +1245,7 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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// Do we have a frame pointer and/or base pointer for this function?
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bool HasFP = hasFP(MF);
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bool HasBP = RegInfo->hasBasePointer(MF);
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bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI();
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unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
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unsigned BPReg = RegInfo->getBaseRegister(MF);
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@ -1202,6 +1258,8 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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: PPC::LWZ );
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const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
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: PPC::LIS );
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const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
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: PPC::OR );
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const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
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: PPC::ORI );
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const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
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@ -1223,7 +1281,6 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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if (HasFP) {
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if (isSVR4ABI) {
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MachineFrameInfo &MFI = MF.getFrameInfo();
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int FPIndex = FI->getFramePointerSaveIndex();
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assert(FPIndex && "No Frame Pointer Save Slot!");
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FPOffset = MFI.getObjectOffset(FPIndex);
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@ -1235,7 +1292,6 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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int BPOffset = 0;
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if (HasBP) {
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if (isSVR4ABI) {
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MachineFrameInfo &MFI = MF.getFrameInfo();
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int BPIndex = FI->getBasePointerSaveIndex();
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assert(BPIndex && "No Base Pointer Save Slot!");
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BPOffset = MFI.getObjectOffset(BPIndex);
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@ -1246,7 +1302,6 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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int PBPOffset = 0;
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if (FI->usesPICBase()) {
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MachineFrameInfo &MFI = MF.getFrameInfo();
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int PBPIndex = FI->getPICBasePointerSaveIndex();
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assert(PBPIndex && "No PIC Base Pointer Save Slot!");
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PBPOffset = MFI.getObjectOffset(PBPIndex);
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@ -1282,9 +1337,25 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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// indexed into with a simple LD/LWZ immediate offset operand.
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bool isLargeFrame = !isInt<16>(FrameSize);
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// On targets without red zone, the SP needs to be restored last, so that
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// all live contents of the stack frame are upwards of the SP. This means
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// that we cannot restore SP just now, since there may be more registers
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// to restore from the stack frame (e.g. R31). If the frame size is not
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// a simple immediate value, we will need a spare register to hold the
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// restored SP. If the frame size is known and small, we can simply adjust
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// the offsets of the registers to be restored, and still use SP to restore
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// them. In such case, the final update of SP will be to add the frame
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// size to it.
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// To simplify the code, set RBReg to the base register used to restore
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// values from the stack, and set SPAdd to the value that needs to be added
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// to the SP at the end. The default values are as if red zone was present.
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unsigned RBReg = SPReg;
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unsigned SPAdd = 0;
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if (FrameSize) {
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// In the prologue, the loaded (or persistent) stack pointer value is offset
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// by the STDU/STDUX/STWU/STWUX instruction. Add this offset back now.
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// In the prologue, the loaded (or persistent) stack pointer value is
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// offset by the STDU/STDUX/STWU/STWUX instruction. For targets with red
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// zone add this offset back now.
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// If this function contained a fastcc call and GuaranteedTailCallOpt is
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// enabled (=> hasFastCall()==true) the fastcc call might contain a tail
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@ -1292,8 +1363,10 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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// value of R31 in this case.
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if (FI->hasFastCall()) {
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assert(HasFP && "Expecting a valid frame pointer.");
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if (!HasRedZone)
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RBReg = FPReg;
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if (!isLargeFrame) {
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BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
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BuildMI(MBB, MBBI, dl, AddImmInst, RBReg)
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.addReg(FPReg).addImm(FrameSize);
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} else {
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BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
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@ -1302,27 +1375,55 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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.addReg(ScratchReg, RegState::Kill)
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.addImm(FrameSize & 0xFFFF);
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BuildMI(MBB, MBBI, dl, AddInst)
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.addReg(SPReg)
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.addReg(RBReg)
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.addReg(FPReg)
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.addReg(ScratchReg);
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}
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} else if (!isLargeFrame && !HasBP && !MFI.hasVarSizedObjects()) {
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BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
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.addReg(SPReg)
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.addImm(FrameSize);
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if (HasRedZone) {
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BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
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.addReg(SPReg)
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.addImm(FrameSize);
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} else {
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// Make sure that adding FrameSize will not overflow the max offset
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// size.
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assert(FPOffset <= 0 && BPOffset <= 0 && PBPOffset <= 0 &&
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"Local offsets should be negative");
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SPAdd = FrameSize;
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FPOffset += FrameSize;
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BPOffset += FrameSize;
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PBPOffset += FrameSize;
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}
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} else {
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BuildMI(MBB, MBBI, dl, LoadInst, SPReg)
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// We don't want to use ScratchReg as a base register, because it
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// could happen to be R0. Use FP instead, but make sure to preserve it.
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if (!HasRedZone) {
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// If FP is not saved, copy it to ScratchReg.
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if (!HasFP)
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BuildMI(MBB, MBBI, dl, OrInst, ScratchReg)
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.addReg(FPReg)
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.addReg(FPReg);
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RBReg = FPReg;
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}
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BuildMI(MBB, MBBI, dl, LoadInst, RBReg)
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.addImm(0)
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.addReg(SPReg);
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}
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}
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assert(RBReg != ScratchReg && "Should have avoided ScratchReg");
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// If there is no red zone, ScratchReg may be needed for holding a useful
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// value (although not the base register). Make sure it is not overwritten
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// too early.
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assert((isPPC64 || !MustSaveCR) &&
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"Epilogue CR restoring supported only in 64-bit mode");
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// If we need to save both the LR and the CR and we only have one available
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// scratch register, we must do them one at a time.
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// If we need to restore both the LR and the CR and we only have one
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// available scratch register, we must do them one at a time.
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if (MustSaveCR && SingleScratchReg && MustSaveLR) {
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// Here TempReg == ScratchReg, and in the absence of red zone ScratchReg
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// is live here.
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assert(HasRedZone && "Expecting red zone");
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BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
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.addImm(8)
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.addReg(SPReg);
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@ -1331,33 +1432,77 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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.addReg(TempReg, getKillRegState(i == e-1));
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}
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if (MustSaveLR)
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// Delay restoring of the LR if ScratchReg is needed. This is ok, since
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// LR is stored in the caller's stack frame. ScratchReg will be needed
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// if RBReg is anything other than SP. We shouldn't use ScratchReg as
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// a base register anyway, because it may happen to be R0.
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bool LoadedLR = false;
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if (MustSaveLR && RBReg == SPReg && isInt<16>(LROffset+SPAdd)) {
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BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
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.addImm(LROffset)
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.addReg(SPReg);
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.addImm(LROffset+SPAdd)
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.addReg(RBReg);
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LoadedLR = true;
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}
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if (MustSaveCR &&
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!(SingleScratchReg && MustSaveLR)) // will only occur for PPC64
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if (MustSaveCR && !(SingleScratchReg && MustSaveLR)) {
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// This will only occur for PPC64.
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assert(isPPC64 && "Expecting 64-bit mode");
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assert(RBReg == SPReg && "Should be using SP as a base register");
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BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
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.addImm(8)
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.addReg(SPReg);
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.addReg(RBReg);
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}
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if (HasFP)
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BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
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.addImm(FPOffset)
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.addReg(SPReg);
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if (HasFP) {
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// If there is red zone, restore FP directly, since SP has already been
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// restored. Otherwise, restore the value of FP into ScratchReg.
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if (HasRedZone || RBReg == SPReg)
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BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
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.addImm(FPOffset)
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.addReg(SPReg);
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else
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BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
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.addImm(FPOffset)
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.addReg(RBReg);
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}
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if (FI->usesPICBase())
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// FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
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BuildMI(MBB, MBBI, dl, LoadInst)
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.addReg(PPC::R30)
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.addImm(PBPOffset)
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.addReg(SPReg);
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.addReg(RBReg);
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if (HasBP)
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BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
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.addImm(BPOffset)
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.addReg(SPReg);
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.addReg(RBReg);
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// There is nothing more to be loaded from the stack, so now we can
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// restore SP: SP = RBReg + SPAdd.
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if (RBReg != SPReg || SPAdd != 0) {
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assert(!HasRedZone && "This should not happen with red zone");
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// If SPAdd is 0, generate a copy.
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if (SPAdd == 0)
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BuildMI(MBB, MBBI, dl, OrInst, SPReg)
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.addReg(RBReg)
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.addReg(RBReg);
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else
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BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
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.addReg(RBReg)
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.addImm(SPAdd);
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assert(RBReg != ScratchReg && "Should be using FP or SP as base register");
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if (RBReg == FPReg)
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BuildMI(MBB, MBBI, dl, OrInst, FPReg)
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.addReg(ScratchReg)
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.addReg(ScratchReg);
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// Now load the LR from the caller's stack frame.
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if (MustSaveLR && !LoadedLR)
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BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
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.addImm(LROffset)
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.addReg(SPReg);
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}
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if (MustSaveCR &&
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!(SingleScratchReg && MustSaveLR)) // will only occur for PPC64
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@ -25,7 +25,7 @@ entry:
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; LARGE-BSS-DAG: lwz [[VREG:[0-9]+]], [[VREF:\.LC[0-9]+]]-.LTOC(30)
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; LARGE-BSS-DAG: lwz {{[0-9]+}}, 0([[VREG]])
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; LARGE-BSS-DAG: stw {{[0-9]+}}, 8(1)
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; LARGE-BSS: lwz 30, -8(1)
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; LARGE-BSS: lwz 30, 24(1)
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; LARGE-BSS: [[VREF]]:
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; LARGE-BSS-NEXT: .p2align 2
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; LARGE-BSS-NEXT: .long bar
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@ -21,4 +21,4 @@ entry:
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; SMALL-BSS-DAG: lwz [[VREG:[0-9]+]], bar@GOT(30)
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; SMALL-BSS-DAG: lwz {{[0-9]+}}, 0([[VREG]])
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; SMALL-BSS: bl call_foo@PLT
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; SMALL-BSS: lwz 30, -8(1)
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; SMALL-BSS: lwz 30, 24(1)
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146
test/CodeGen/PowerPC/stack-no-redzone.ll
Normal file
146
test/CodeGen/PowerPC/stack-no-redzone.ll
Normal file
@ -0,0 +1,146 @@
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; Test that accesses of the stack remain within the range defined by R1,
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; i.e. that loads and stores only access the allocated stack. This does not
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; have to be the case when red zone is present.
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|
||||
; Make sure that there is no red zone, i.e. ppc32 and SVR4 ABI.
|
||||
; RUN: llc -mtriple=powerpc--freebsd-elf < %s | FileCheck %s
|
||||
|
||||
; There are two ways that the stack pointer can be adjusted in the prologue:
|
||||
; - by adding an immediate value:
|
||||
; stwu r1, -imm(r1)
|
||||
; - by adding another register:
|
||||
; stwux r1, rx, r1
|
||||
;
|
||||
; The restoring of the stack pointer can be done:
|
||||
; - by adding an immediate value to it:
|
||||
; addi r1, r1, imm
|
||||
; - by copying the value from another register:
|
||||
; mr r1, rx
|
||||
|
||||
|
||||
; Nothing (no special features).
|
||||
;
|
||||
; CHECK-LABEL: test_n:
|
||||
; CHECK-NOT: stw {{[0-9]+}}, -{{[0-9]+}}(1)
|
||||
; CHECK: stwu 1, -[[SIZE:[0-9]+]](1)
|
||||
; CHECK: addi 1, 1, [[SIZE]]
|
||||
; CHECK-NOT: lwz {{[0-9]+}}, -{{[0-9]+}}(1)
|
||||
define i32 @test_n() local_unnamed_addr #0 {
|
||||
entry:
|
||||
%t0 = tail call i32 bitcast (i32 (...)* @bar0 to i32 ()*)() #0
|
||||
ret i32 %t0
|
||||
}
|
||||
|
||||
; Aligned object on the stack.
|
||||
;
|
||||
; CHECK-LABEL: test_a:
|
||||
; CHECK-NOT: stw {{[0-9]+}}, -{{[0-9]+}}(1)
|
||||
; CHECK: stwux 1, 1, {{[0-9]+}}
|
||||
; CHECK: mr 1, {{[0-9]+}}
|
||||
; CHECK-NOT: lwz {{[0-9]+}}, -{{[0-9]+}}(1)
|
||||
|
||||
define i32 @test_a() local_unnamed_addr #0 {
|
||||
entry:
|
||||
%t0 = alloca i32, align 128
|
||||
%t1 = tail call i32 bitcast (i32 (...)* @bar1 to i32 (i32*)*)(i32* %t0) #0
|
||||
ret i32 %t1
|
||||
}
|
||||
|
||||
; Dynamic allocation on the stack.
|
||||
;
|
||||
; CHECK-LABEL: test_d:
|
||||
; CHECK-NOT: stw {{[0-9]+}}, -{{[0-9]+}}(1)
|
||||
; CHECK: stwu 1, -[[SIZE:[0-9]+]](1)
|
||||
; CHECK: mr 1, {{[0-9]+}}
|
||||
; CHECK-NOT: lwz {{[0-9]+}}, -{{[0-9]+}}(1)
|
||||
define i32 @test_d(i32 %p0) local_unnamed_addr #0 {
|
||||
%t0 = alloca i32, i32 %p0, align 4
|
||||
%t1 = tail call i32 bitcast (i32 (...)* @bar1 to i32 (i32*)*)(i32* %t0) #0
|
||||
ret i32 %t1
|
||||
}
|
||||
|
||||
; Large stack (exceeds size of D-field).
|
||||
; CHECK-LABEL: test_s:
|
||||
; CHECK-NOT: stw {{[0-9]+}}, -{{[0-9]+}}(1)
|
||||
; CHECK: stwux 1, 1, {{[0-9]+}}
|
||||
; CHECK: mr 1, {{[0-9]+}}
|
||||
; CHECK-NOT: lwz {{[0-9]+}}, -{{[0-9]+}}(1)
|
||||
define i32 @test_s(i32 %p0) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%t0 = alloca [16384 x i32]
|
||||
%t1 = getelementptr [16384 x i32], [16384 x i32]* %t0, i32 0, i32 0
|
||||
%t2 = tail call i32 bitcast (i32 (...)* @bar1 to i32 (i32*)*)(i32* %t1) #0
|
||||
ret i32 %t2
|
||||
}
|
||||
|
||||
; Combinations.
|
||||
|
||||
; CHECK-LABEL: test_ad:
|
||||
; CHECK-NOT: stw {{[0-9]+}}, -{{[0-9]+}}(1)
|
||||
; CHECK: stwux 1, 1, {{[0-9]+}}
|
||||
; CHECK: mr 1, {{[0-9]+}}
|
||||
; CHECK-NOT: lwz {{[0-9]+}}, -{{[0-9]+}}(1)
|
||||
define i32 @test_ad(i32 %p0) local_unnamed_addr #0 {
|
||||
%t0 = alloca i32, align 128
|
||||
%t1 = alloca i32, i32 %p0, align 4
|
||||
%t2 = tail call i32 bitcast (i32 (...)* @bar1 to i32 (i32*)*)(i32* %t0) #0
|
||||
%t3 = tail call i32 bitcast (i32 (...)* @bar1 to i32 (i32*)*)(i32* %t1) #0
|
||||
%t4 = add i32 %t2, %t3
|
||||
ret i32 %t4
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_as:
|
||||
; CHECK-NOT: stw {{[0-9]+}}, -{{[0-9]+}}(1)
|
||||
; CHECK: stwux 1, 1, {{[0-9]+}}
|
||||
; CHECK: mr 1, {{[0-9]+}}
|
||||
; CHECK-NOT: lwz {{[0-9]+}}, -{{[0-9]+}}(1)
|
||||
define i32 @test_as() local_unnamed_addr #0 {
|
||||
%t0 = alloca i32, align 128
|
||||
%t1 = alloca [16384 x i32]
|
||||
%t2 = tail call i32 bitcast (i32 (...)* @bar1 to i32 (i32*)*)(i32* %t0) #0
|
||||
%t3 = getelementptr [16384 x i32], [16384 x i32]* %t1, i32 0, i32 0
|
||||
%t4 = tail call i32 bitcast (i32 (...)* @bar1 to i32 (i32*)*)(i32* %t3) #0
|
||||
%t5 = add i32 %t2, %t4
|
||||
ret i32 %t5
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_ds:
|
||||
; CHECK-NOT: stw {{[0-9]+}}, -{{[0-9]+}}(1)
|
||||
; CHECK: stwux 1, 1, {{[0-9]+}}
|
||||
; CHECK: mr 1, {{[0-9]+}}
|
||||
; CHECK-NOT: lwz {{[0-9]+}}, -{{[0-9]+}}(1)
|
||||
define i32 @test_ds(i32 %p0) local_unnamed_addr #0 {
|
||||
%t0 = alloca i32, i32 %p0, align 4
|
||||
%t1 = alloca [16384 x i32]
|
||||
%t2 = tail call i32 bitcast (i32 (...)* @bar1 to i32 (i32*)*)(i32* %t0) #0
|
||||
%t3 = getelementptr [16384 x i32], [16384 x i32]* %t1, i32 0, i32 0
|
||||
%t4 = tail call i32 bitcast (i32 (...)* @bar1 to i32 (i32*)*)(i32* %t3) #0
|
||||
%t5 = add i32 %t2, %t4
|
||||
ret i32 %t5
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_ads:
|
||||
; CHECK-NOT: stw {{[0-9]+}}, -{{[0-9]+}}(1)
|
||||
; CHECK: stwux 1, 1, {{[0-9]+}}
|
||||
; CHECK: mr 1, {{[0-9]+}}
|
||||
; CHECK-NOT: lwz {{[0-9]+}}, -{{[0-9]+}}(1)
|
||||
define i32 @test_ads(i32 %p0) local_unnamed_addr #0 {
|
||||
%t0 = alloca i32, align 128
|
||||
%t1 = alloca i32, i32 %p0, align 4
|
||||
%t2 = alloca [16384 x i32]
|
||||
|
||||
%t3 = tail call i32 bitcast (i32 (...)* @bar1 to i32 (i32*)*)(i32* %t0) #0
|
||||
%t4 = tail call i32 bitcast (i32 (...)* @bar1 to i32 (i32*)*)(i32* %t1) #0
|
||||
%t5 = add i32 %t3, %t4
|
||||
|
||||
%t6 = getelementptr [16384 x i32], [16384 x i32]* %t2, i32 0, i32 0
|
||||
%t7 = tail call i32 bitcast (i32 (...)* @bar1 to i32 (i32*)*)(i32* %t6) #0
|
||||
%t8 = add i32 %t5, %t7
|
||||
ret i32 %t7
|
||||
}
|
||||
|
||||
|
||||
declare i32 @bar0(...) local_unnamed_addr #0
|
||||
declare i32 @bar1(...) local_unnamed_addr #0
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
@ -83,18 +83,26 @@ entry:
|
||||
; CHECK-32-DAG: subfic 0, [[REG]], -64
|
||||
; CHECK-32: stwux 1, 1, 0
|
||||
; CHECK-32: subf 0, 0, 1
|
||||
; CHECK-32: stw 30, -8(0)
|
||||
; CHECK-32: mr 30, 0
|
||||
; CHECK-32: addic 0, 0, -4
|
||||
; CHECK-32: stwx 31, 0, 0
|
||||
; CHECK-32: addic 0, 0, -4
|
||||
; CHECK-32: stwx 30, 0, 0
|
||||
; CHECK-32: addic 30, 0, 8
|
||||
|
||||
; CHECK-32-PIC-LABEL: @goo
|
||||
; CHECK-32-PIC-DAG: mflr [[LR:[0-9]+]]
|
||||
; CHECK-32-PIC-DAG: clrlwi [[REG:[0-9]+]], 1, 27
|
||||
; CHECK-32-PIC-DAG: stw [[LR]], 4(1)
|
||||
; CHECK-32-PIC-DAG: subfic 0, [[REG]], -64
|
||||
; CHECK-32-PIC: stwux 1, 1, 0
|
||||
; CHECK-32-PIC: subf 0, 0, 1
|
||||
; CHECK-32-PIC: stw 29, -12(0)
|
||||
; CHECK-32-PIC-DAG: mr 29, 0
|
||||
; CHECK-32-PIC: stwux 1, 1, 0
|
||||
; CHECK-32-PIC: subf 0, 0, 1
|
||||
; CHECK-32-PIC: addic 0, 0, -4
|
||||
; CHECK-32-PIC: stwx 31, 0, 0
|
||||
; CHECK-32-PIC: addic 0, 0, -4
|
||||
; CHECK-32-PIC: stwx 30, 0, 0
|
||||
; CHECK-32-PIC: addic 0, 0, -4
|
||||
; CHECK-32-PIC: stwx 29, 0, 0
|
||||
; CHECK-32-PIC: addic 29, 0, 12
|
||||
|
||||
; The large-frame-size case.
|
||||
define void @hoo(%struct.s* byval nocapture readonly %a) {
|
||||
@ -138,9 +146,11 @@ entry:
|
||||
; CHECK-32-DAG: subfc 0, [[REG3]], [[REG2]]
|
||||
; CHECK-32: stwux 1, 1, 0
|
||||
; CHECK-32: subf 0, 0, 1
|
||||
; CHECK-32-DAG: stw 31, -4(0)
|
||||
; CHECK-32-DAG: stw 30, -8(0)
|
||||
; CHECK-32: mr 30, 0
|
||||
; CHECK-32: addic 0, 0, -4
|
||||
; CHECK-32: stwx 31, 0, 0
|
||||
; CHECK-32: addic 0, 0, -4
|
||||
; CHECK-32: stwx 30, 0, 0
|
||||
; CHECK-32: addic 30, 0, 8
|
||||
|
||||
; CHECK-32: blr
|
||||
|
||||
@ -152,10 +162,13 @@ entry:
|
||||
; CHECK-32-PIC-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904
|
||||
; CHECK-32-PIC-DAG: stw 0, 4(1)
|
||||
; CHECK-32-PIC-DAG: subfc 0, [[REG3]], [[REG2]]
|
||||
; CHECK-32-PIC: stwux 1, 1, 0
|
||||
; CHECK-32-PIC: stw 29, -12(0)
|
||||
; CHECK-32-PIC: subf 0, 0, 1
|
||||
; CHECK-32-PIC: mr 29, 0
|
||||
; CHECK-32-PIC: stwux 1, 1, 0
|
||||
; CHECK-32-PIC: subf 0, 0, 1
|
||||
; CHECK-32-PIC: addic 0, 0, -4
|
||||
; CHECK-32-PIC: stwx 31, 0, 0
|
||||
; CHECK-32-PIC: addic 0, 0, -8
|
||||
; CHECK-32-PIC: stwx 29, 0, 0
|
||||
; CHECK-32-PIC: addic 29, 0, 12
|
||||
|
||||
; CHECK-32: blr
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user