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Fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)), to simplify some code

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that SCEVExpander can produce when running on behalf of LSR.

llvm-svn: 93949
This commit is contained in:
Dan Gohman 2010-01-19 23:30:49 +00:00
parent 5daaa4b21c
commit 34b548b94a
2 changed files with 37 additions and 0 deletions
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20
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -1088,6 +1088,26 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
if (Result.getNode()) return Result;
}
// fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
if (N1.getOpcode() == ISD::SHL &&
N1.getOperand(0).getOpcode() == ISD::SUB)
if (ConstantSDNode *C =
dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
if (C->getAPIntValue() == 0)
return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
N1.getOperand(0).getOperand(1),
N1.getOperand(1)));
if (N0.getOpcode() == ISD::SHL &&
N0.getOperand(0).getOpcode() == ISD::SUB)
if (ConstantSDNode *C =
dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
if (C->getAPIntValue() == 0)
return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1,
DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
N0.getOperand(0).getOperand(1),
N0.getOperand(1)));
return SDValue();
}

17
test/CodeGen/X86/neg-shl-add.ll Normal file
View File

@ -0,0 +1,17 @@
; RUN: llc -march=x86-64 < %s | not grep negq
; These sequences don't need neg instructions; they can be done with
; a single shift and sub each.
define i64 @foo(i64 %x, i64 %y, i64 %n) nounwind {
%a = sub i64 0, %y
%b = shl i64 %a, %n
%c = add i64 %b, %x
ret i64 %c
}
define i64 @boo(i64 %x, i64 %y, i64 %n) nounwind {
%a = sub i64 0, %y
%b = shl i64 %a, %n
%c = add i64 %x, %b
ret i64 %c
}