mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-12-04 17:56:53 +00:00
Eliminate a 'tst' that immediately follows an 'and'
by morphing the 'and' to its recording form 'andS'. This is basically a test commit into this area, to see whether the bots like me. Several generalizations can be applied and various avenues of code simplification are open. I'll introduce those as I go. I am aware of stylistic input from Bill Wendling, about where put the analysis complexity, but I am positive that we can move things around easily and will find a satisfactory solution. llvm-svn: 113839
This commit is contained in:
parent
40a8053a15
commit
357e2fe748
@ -1372,6 +1372,19 @@ AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpValue) const {
|
||||
SrcReg = MI->getOperand(0).getReg();
|
||||
CmpValue = MI->getOperand(1).getImm();
|
||||
return true;
|
||||
case ARM::TSTri: {
|
||||
if (MI->getParent()->begin() == MachineBasicBlock::const_iterator(MI))
|
||||
return false;
|
||||
const MachineInstr *AND = llvm::prior(MI);
|
||||
if (AND->getOpcode() != ARM::ANDri)
|
||||
return false;
|
||||
if (MI->getOperand(0).getReg() == AND->getOperand(1).getReg() &&
|
||||
MI->getOperand(1).getImm() == AND->getOperand(2).getImm()) {
|
||||
SrcReg = AND->getOperand(0).getReg();
|
||||
CmpValue = 0;
|
||||
return true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
@ -1421,6 +1434,8 @@ OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpValue,
|
||||
switch (MI->getOpcode()) {
|
||||
default: break;
|
||||
case ARM::ADDri:
|
||||
case ARM::ANDri:
|
||||
case ARM::t2ANDri:
|
||||
case ARM::SUBri:
|
||||
case ARM::t2ADDri:
|
||||
case ARM::t2SUBri:
|
||||
|
Loading…
Reference in New Issue
Block a user