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[AArch64] Optimize floating point materialization
This patch changes isFPImmLegal to return if the value can be enconded as the immediate operand of a logical instruction besides checking if for immediate field for fmov. This optimizes some floating point materization, inclusive values used on isinf lowering. Reviewed By: rengolin, efriedma, evandro Differential Revision: https://reviews.llvm.org/D57044 llvm-svn: 352866
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@ -405,10 +405,9 @@ unsigned AArch64FastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
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bool Is64Bit = (VT == MVT::f64);
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// This checks to see if we can use FMOV instructions to materialize
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// a constant, otherwise we have to materialize via the constant pool.
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if (TLI.isFPImmLegal(Val, VT)) {
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int Imm =
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Is64Bit ? AArch64_AM::getFP64Imm(Val) : AArch64_AM::getFP32Imm(Val);
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assert((Imm != -1) && "Cannot encode floating-point constant.");
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int Imm =
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Is64Bit ? AArch64_AM::getFP64Imm(Val) : AArch64_AM::getFP32Imm(Val);
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if (Imm != -1) {
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unsigned Opc = Is64Bit ? AArch64::FMOVDi : AArch64::FMOVSi;
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return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm);
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}
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@ -5424,34 +5424,30 @@ bool AArch64TargetLowering::isOffsetFoldingLegal(
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}
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bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
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// We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
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// FIXME: We should be able to handle f128 as well with a clever lowering.
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if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32 ||
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(VT == MVT::f16 && Subtarget->hasFullFP16()))) {
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LLVM_DEBUG(dbgs() << "Legal " << VT.getEVTString() << " imm value: 0\n");
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return true;
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}
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bool IsLegal = false;
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SmallString<128> ImmStrVal;
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Imm.toString(ImmStrVal);
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// We can materialize #0.0 as fmov $Rd, XZR for 64-bit, 32-bit cases, and
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// 16-bit case when target has full fp16 support.
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// FIXME: We should be able to handle f128 as well with a clever lowering.
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const APInt ImmInt = Imm.bitcastToAPInt();
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if (VT == MVT::f64)
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IsLegal = AArch64_AM::getFP64Imm(Imm) != -1;
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IsLegal = AArch64_AM::getFP64Imm(ImmInt) != -1 || Imm.isPosZero();
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else if (VT == MVT::f32)
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IsLegal = AArch64_AM::getFP32Imm(Imm) != -1;
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IsLegal = AArch64_AM::getFP32Imm(ImmInt) != -1 || Imm.isPosZero();
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else if (VT == MVT::f16 && Subtarget->hasFullFP16())
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IsLegal = AArch64_AM::getFP16Imm(Imm) != -1;
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IsLegal = AArch64_AM::getFP16Imm(ImmInt) != -1 || Imm.isPosZero();
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// TODO: fmov h0, w0 is also legal, however on't have an isel pattern to
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// generate that fmov.
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if (IsLegal) {
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LLVM_DEBUG(dbgs() << "Legal " << VT.getEVTString()
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<< " imm value: " << ImmStrVal << "\n");
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return true;
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}
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// If we can not materialize in immediate field for fmov, check if the
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// value can be encoded as the immediate operand of a logical instruction.
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// The immediate value will be created with either MOVZ, MOVN, or ORR.
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if (!IsLegal && (VT == MVT::f64 || VT == MVT::f32))
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IsLegal = AArch64_AM::isAnyMOVWMovAlias(ImmInt.getZExtValue(),
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VT.getSizeInBits());
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LLVM_DEBUG(dbgs() << "Illegal " << VT.getEVTString()
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<< " imm value: " << ImmStrVal << "\n");
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return false;
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LLVM_DEBUG(dbgs() << (IsLegal ? "Legal " : "Illegal ") << VT.getEVTString()
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<< " imm value: "; Imm.dump(););
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return IsLegal;
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}
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//===----------------------------------------------------------------------===//
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@ -22,11 +22,11 @@ define double @not_fabs(double %x) #0 {
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define float @still_not_fabs(float %x) #0 {
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; CHECK-LABEL: still_not_fabs:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI1_0
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; CHECK-NEXT: ldr s1, [x8, :lo12:.LCPI1_0]
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; CHECK-NEXT: fneg s2, s0
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; CHECK-NEXT: fcmp s0, s1
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; CHECK-NEXT: fcsel s0, s0, s2, ge
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; CHECK-NEXT: orr w8, wzr, #0x80000000
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; CHECK-NEXT: fmov s2, w8
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; CHECK-NEXT: fneg s1, s0
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; CHECK-NEXT: fcmp s0, s2
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; CHECK-NEXT: fcsel s0, s0, s1, ge
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; CHECK-NEXT: ret
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%cmp = fcmp nnan oge float %x, -0.0
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%sub = fsub nnan float -0.0, %x
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@ -132,13 +132,13 @@ define double @test7(double %a, double %b) nounwind {
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define float @fadd_const_multiuse_fmf(float %x) {
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; CHECK-LABEL: fadd_const_multiuse_fmf:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI10_0
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; CHECK-NEXT: adrp x9, .LCPI10_1
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; CHECK-NEXT: ldr s1, [x8, :lo12:.LCPI10_0]
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; CHECK-NEXT: ldr s2, [x9, :lo12:.LCPI10_1]
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; CHECK-NEXT: fadd s1, s0, s1
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; CHECK-NEXT: fadd s0, s0, s2
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; CHECK-NEXT: fadd s0, s1, s0
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; CHECK-DAG: mov [[W59:w[0-9]+]], #1114374144
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; CHECK-DAG: mov [[W42:w[0-9]+]], #1109917696
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; CHECK-DAG: fmov [[FP59:s[0-9]+]], [[W59]]
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; CHECK-DAG: fmov [[FP42:s[0-9]+]], [[W42]]
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; CHECK-NEXT: fadd [[TMP1:s[0-9]+]], s0, [[FP42]]
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; CHECK-NEXT: fadd [[TMP2:s[0-9]+]], s0, [[FP59]]
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; CHECK-NEXT: fadd s0, [[TMP1]], [[TMP2]]
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; CHECK-NEXT: ret
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%a1 = fadd float %x, 42.0
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%a2 = fadd nsz reassoc float %a1, 17.0
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@ -153,13 +153,13 @@ define float @fadd_const_multiuse_fmf(float %x) {
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define float @fadd_const_multiuse_attr(float %x) #0 {
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; CHECK-LABEL: fadd_const_multiuse_attr:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x9, .LCPI11_1
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; CHECK-NEXT: adrp x8, .LCPI11_0
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; CHECK-NEXT: ldr s1, [x9, :lo12:.LCPI11_1]
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; CHECK-NEXT: ldr s2, [x8, :lo12:.LCPI11_0]
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; CHECK-NEXT: fadd s1, s0, s1
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; CHECK-NEXT: fadd s1, s2, s1
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; CHECK-NEXT: fadd s0, s0, s1
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; CHECK-DAG: mov [[W59:w[0-9]+]], #1114374144
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; CHECK-DAG: mov [[W17:w[0-9]+]], #1109917696
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; CHECK-NEXT: fmov [[FP59:s[0-9]+]], [[W59]]
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; CHECK-NEXT: fmov [[FP17:s[0-9]+]], [[W17]]
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; CHECK-NEXT: fadd [[TMP1:s[0-9]+]], s0, [[FP59]]
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; CHECK-NEXT: fadd [[TMP2:s[0-9]+]], [[FP17]], [[TMP1]]
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; CHECK-NEXT: fadd s0, s0, [[TMP2]]
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; CHECK-NEXT: ret
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%a1 = fadd float %x, 42.0
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%a2 = fadd float %a1, 17.0
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@ -18,8 +18,10 @@ define void @check_float() {
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%newval2 = fadd float %val, 128.0
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store volatile float %newval2, float* @varf32
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; CHECK-DAG: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.LCPI0_0
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; TINY-DAG: ldr {{s[0-9]+}}, .LCPI0_0
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; CHECK-DAG: mov [[W128:w[0-9]+]], #1124073472
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; CHECK-DAG: fmov {{s[0-9]+}}, [[W128]]
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; TINY-DAG: mov [[W128:w[0-9]+]], #1124073472
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; TINY-DAG: fmov {{s[0-9]+}}, [[W128]]
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; CHECK: ret
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; TINY: ret
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@ -38,8 +40,10 @@ define void @check_double() {
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%newval2 = fadd double %val, 128.0
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store volatile double %newval2, double* @varf64
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; CHECK-DAG: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.LCPI1_0
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; TINY-DAG: ldr {{d[0-9]+}}, .LCPI1_0
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; CHECK-DAG: mov [[X128:x[0-9]+]], #4638707616191610880
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; CHECK-DAG: fmov {{d[0-9]+}}, [[X128]]
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; TINY-DAG: mov [[X128:x[0-9]+]], #4638707616191610880
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; TINY-DAG: fmov {{d[0-9]+}}, [[X128]]
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; CHECK: ret
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; TINY: ret
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62
test/CodeGen/AArch64/isinf.ll
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62
test/CodeGen/AArch64/isinf.ll
Normal file
@ -0,0 +1,62 @@
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; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon,+fullfp16 < %s -o -| FileCheck %s
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declare half @llvm.fabs.f16(half)
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declare float @llvm.fabs.f32(float)
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declare double @llvm.fabs.f64(double)
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declare fp128 @llvm.fabs.f128(fp128)
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; INFINITY requires loading the constant for _Float16
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define i32 @replace_isinf_call_f16(half %x) {
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; CHECK-LABEL: replace_isinf_call_f16:
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; CHECK: adrp [[ADDR:x[0-9]+]], [[CSTLABEL:.LCP.*]]
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; CHECK: ldr [[INFINITY:h[0-9]+]], {{[[]}}[[ADDR]], :lo12:[[CSTLABEL]]{{[]]}}
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; CHECK-NEXT: fabs [[ABS:h[0-9]+]], h0
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; CHECK-NEXT: fcmp [[ABS]], [[INFINITY]]
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; CHECK-NEXT: cset w0, eq
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%abs = tail call half @llvm.fabs.f16(half %x)
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%cmpinf = fcmp oeq half %abs, 0xH7C00
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%ret = zext i1 %cmpinf to i32
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ret i32 %ret
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}
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; Check if INFINITY for float is materialized
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define i32 @replace_isinf_call_f32(float %x) {
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; CHECK-LABEL: replace_isinf_call_f32:
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; CHECK: orr [[INFSCALARREG:w[0-9]+]], wzr, #0x7f800000
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; CHECK-NEXT: fabs [[ABS:s[0-9]+]], s0
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; CHECK-NEXT: fmov [[INFREG:s[0-9]+]], [[INFSCALARREG]]
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; CHECK-NEXT: fcmp [[ABS]], [[INFREG]]
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; CHECK-NEXT: cset w0, eq
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%abs = tail call float @llvm.fabs.f32(float %x)
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%cmpinf = fcmp oeq float %abs, 0x7FF0000000000000
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%ret = zext i1 %cmpinf to i32
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ret i32 %ret
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}
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; Check if INFINITY for double is materialized
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define i32 @replace_isinf_call_f64(double %x) {
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; CHECK-LABEL: replace_isinf_call_f64:
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; CHECK: orr [[INFSCALARREG:x[0-9]+]], xzr, #0x7ff0000000000000
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; CHECK-NEXT: fabs [[ABS:d[0-9]+]], d0
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; CHECK-NEXT: fmov [[INFREG:d[0-9]+]], [[INFSCALARREG]]
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; CHECK-NEXT: fcmp [[ABS]], [[INFREG]]
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; CHECK-NEXT: cset w0, eq
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%abs = tail call double @llvm.fabs.f64(double %x)
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%cmpinf = fcmp oeq double %abs, 0x7FF0000000000000
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%ret = zext i1 %cmpinf to i32
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ret i32 %ret
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}
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; For long double it still requires loading the constant.
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define i32 @replace_isinf_call_f128(fp128 %x) {
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; CHECK-LABEL: replace_isinf_call_f128:
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; CHECK: adrp [[ADDR:x[0-9]+]], [[CSTLABEL:.LCP.*]]
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; CHECK: ldr q1, {{[[]}}[[ADDR]], :lo12:[[CSTLABEL]]{{[]]}}
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; CHECK: bl __eqtf2
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; CHECK: cmp w0, #0
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; CHECK: cset w0, eq
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%abs = tail call fp128 @llvm.fabs.f128(fp128 %x)
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%cmpinf = fcmp oeq fp128 %abs, 0xL00000000000000007FFF000000000000
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%ret = zext i1 %cmpinf to i32
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ret i32 %ret
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}
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@ -28,13 +28,13 @@ define float @fmaxnm(i32 %i1, i32 %i2) #0 {
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define float @not_fmaxnm_maybe_nan(i32 %i1, i32 %i2) #0 {
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; CHECK-LABEL: not_fmaxnm_maybe_nan:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI1_0
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; CHECK-NEXT: ldr s0, [x8, :lo12:.LCPI1_0]
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; CHECK-NEXT: ucvtf s1, w0
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; CHECK-NEXT: ucvtf s2, w1
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; CHECK-NEXT: fmov s3, #17.00000000
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; CHECK-NEXT: fmul s0, s1, s0
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; CHECK-NEXT: fadd s1, s2, s3
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; CHECK-NEXT: orr w8, wzr, #0xff800000
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; CHECK-NEXT: ucvtf s0, w0
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; CHECK-NEXT: ucvtf s1, w1
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; CHECK-NEXT: fmov s2, #17.00000000
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; CHECK-NEXT: fmov s3, w8
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; CHECK-NEXT: fmul s0, s0, s3
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; CHECK-NEXT: fadd s1, s1, s2
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; CHECK-NEXT: fcmp s0, s1
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; CHECK-NEXT: fcsel s0, s0, s1, pl
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; CHECK-NEXT: ret
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@ -13,18 +13,16 @@ define void @floating_lits() {
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%floatval = load float, float* @varfloat
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%newfloat = fadd float %floatval, 128.0
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; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI[0-9]+_[0-9]+]]
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; CHECK: ldr [[LIT128:s[0-9]+]], [x[[LITBASE]], {{#?}}:lo12:[[CURLIT]]]
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; CHECK: mov [[W128:w[0-9]+]], #1124073472
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; CHECK: fmov [[LIT128:s[0-9]+]], [[W128]]
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; CHECK-NOFP-NOT: ldr {{s[0-9]+}},
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; CHECK-TINY: ldr [[LIT128:s[0-9]+]], [[CURLIT:.LCPI[0-9]+_[0-9]+]]
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; CHECK-TINY: mov [[W128:w[0-9]+]], #1124073472
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; CHECK-TINE: fmov [[LIT128:s[0-9]+]], [[W128]]
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; CHECK-NOFP-TINY-NOT: ldr {{s[0-9]+}},
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; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g0_nc:[[CURLIT:.LCPI[0-9]+_[0-9]+]]
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; CHECK-LARGE: movk x[[LITADDR]], #:abs_g1_nc:[[CURLIT]]
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; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]]
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; CHECK-LARGE: movk x[[LITADDR]], #:abs_g3:[[CURLIT]]
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; CHECK-LARGE: ldr {{s[0-9]+}}, [x[[LITADDR]]]
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; CHECK-LARGE: mov [[W128:w[0-9]+]], #1124073472
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; CHECK-LARGE: fmov [[LIT128:s[0-9]+]], [[W128]]
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; CHECK-LARGE: fadd
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; CHECK-NOFP-LARGE-NOT: ldr {{s[0-9]+}},
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; CHECK-NOFP-LARGE-NOT: fadd
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@ -2,22 +2,22 @@
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; RUN: llc < %s -mtriple=aarch64-win32-gnu | FileCheck -check-prefix=MINGW %s
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define double @double() {
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ret double 0x0000000000800000
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ret double 0x0000000000800001
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}
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; CHECK: .globl __real@0000000000800000
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; CHECK-NEXT: .section .rdata,"dr",discard,__real@0000000000800000
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; CHECK: .globl __real@0000000000800001
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; CHECK-NEXT: .section .rdata,"dr",discard,__real@0000000000800001
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; CHECK-NEXT: .p2align 3
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; CHECK-NEXT: __real@0000000000800000:
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; CHECK-NEXT: .xword 8388608
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; CHECK-NEXT: __real@0000000000800001:
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; CHECK-NEXT: .xword 8388609
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; CHECK: double:
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; CHECK: adrp x8, __real@0000000000800000
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; CHECK-NEXT: ldr d0, [x8, __real@0000000000800000]
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; CHECK: adrp x8, __real@0000000000800001
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; CHECK-NEXT: ldr d0, [x8, __real@0000000000800001]
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; CHECK-NEXT: ret
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; MINGW: .section .rdata,"dr"
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; MINGW-NEXT: .p2align 3
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; MINGW-NEXT: [[LABEL:\.LC.*]]:
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; MINGW-NEXT: .xword 8388608
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; MINGW-NEXT: .xword 8388609
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; MINGW: double:
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; MINGW: adrp x8, [[LABEL]]
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; MINGW-NEXT: ldr d0, [x8, [[LABEL]]]
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