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[AArch64] Add ARMv8.2-A ID_A64MMFR2_EL1 register

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ARMv8.2-A adds a new ID register, ID_A64MMFR2_EL1, which behaves in the
same way as ID_A64MMFR0_EL1 and ID_A64MMFR1_EL1. It is a required part
of ARMv8.2-A, so no additional subtarget features are required.

Differential Revision: http://reviews.llvm.org/D15017

llvm-svn: 254155
This commit is contained in:
Oliver Stannard 2015-11-26 15:26:10 +00:00
parent 55e6d9804d
commit 3708d85580
4 changed files with 12 additions and 0 deletions
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1
lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
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@ -192,6 +192,7 @@ const AArch64NamedImmMapper::Mapping AArch64SysReg::MRSMapper::MRSMappings[] = {
{"id_aa64isar1_el1", ID_A64ISAR1_EL1, {}},
{"id_aa64mmfr0_el1", ID_A64MMFR0_EL1, {}},
{"id_aa64mmfr1_el1", ID_A64MMFR1_EL1, {}},
{"id_aa64mmfr2_el1", ID_A64MMFR2_EL1, {AArch64::HasV8_2aOps}},
{"mvfr0_el1", MVFR0_EL1, {}},
{"mvfr1_el1", MVFR1_EL1, {}},
{"mvfr2_el1", MVFR2_EL1, {}},

1
lib/Target/AArch64/Utils/AArch64BaseInfo.h
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@ -594,6 +594,7 @@ namespace AArch64SysReg {
ID_A64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001
ID_A64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000
ID_A64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001
ID_A64MMFR2_EL1 = 0xc03a, // 11 000 0000 0111 010
MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000
MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001
MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010

6
test/MC/AArch64/armv8.2a-mmfr2.s Normal file
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@ -0,0 +1,6 @@
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s | FileCheck %s
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a < %s 2>&1 | FileCheck %s --check-prefix=ERROR
mrs x3, id_aa64mmfr2_el1
// CHECK: mrs x3, ID_AA64MMFR2_EL1 // encoding: [0x43,0x07,0x38,0xd5]
// ERROR: error: expected readable system register

4
test/MC/Disassembler/AArch64/armv8.2a-mmfr2.txt Normal file
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@ -0,0 +1,4 @@
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a --disassemble < %s | FileCheck %s
[0x43,0x07,0x38,0xd5]
# CHECK: mrs x3, ID_AA64MMFR2_EL1