RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-02-04 03:06:28 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[PowerPC] Support R_PPC_REL16 family of relocations

Browse Source 
The GNU assembler supports (as extension to the ABI) use of PC-relative
relocations in half16 fields, which allows writing code like:

  li 1, base-.

This patch adds support for those relocation types in the assembler.

llvm-svn: 184552
This commit is contained in:
Ulrich Weigand 2013-06-21 14:44:37 +00:00
parent d5bb2945ff
commit 3720d45002
4 changed files with 61 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
include/llvm/Object/ELF.h
View File

@ -2053,6 +2053,10 @@ StringRef ELFObjectFile<ELFT>::getRelocationTypeName(uint32_t Type) const {
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_GOT_DTPREL16_LO_DS);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_GOT_DTPREL16_HI);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_GOT_DTPREL16_HA);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_REL16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_REL16_LO);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_REL16_HI);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_REL16_HA);
default: break;
}
break;
@ -2127,6 +2131,10 @@ StringRef ELFObjectFile<ELFT>::getRelocationTypeName(uint32_t Type) const {
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_DTPREL16_HIGHESTA);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_TLSGD);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_TLSLD);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_REL16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_REL16_LO);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_REL16_HI);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_REL16_HA);
default: break;
}
break;

12
include/llvm/Support/ELF.h
View File

@ -484,7 +484,11 @@ enum {
R_PPC_GOT_DTPREL16_DS = 91,
R_PPC_GOT_DTPREL16_LO_DS = 92,
R_PPC_GOT_DTPREL16_HI = 93,
R_PPC_GOT_DTPREL16_HA = 94
R_PPC_GOT_DTPREL16_HA = 94,
R_PPC_REL16 = 249,
R_PPC_REL16_LO = 250,
R_PPC_REL16_HI = 251,
R_PPC_REL16_HA = 252
};
// ELF Relocation types for PPC64
@ -557,7 +561,11 @@ enum {
R_PPC64_DTPREL16_HIGHEST = 105,
R_PPC64_DTPREL16_HIGHESTA = 106,
R_PPC64_TLSGD = 107,
R_PPC64_TLSLD = 108
R_PPC64_TLSLD = 108,
R_PPC64_REL16 = 249,
R_PPC64_REL16_LO = 250,
R_PPC64_REL16_HI = 251,
R_PPC64_REL16_HA = 252
};
// ELF Relocation types for AArch64

17
lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
View File

@ -63,6 +63,23 @@ unsigned PPCELFObjectWriter::getRelocTypeInner(const MCValue &Target,
case PPC::fixup_ppc_brcond14:
Type = ELF::R_PPC_REL14;
break;
case PPC::fixup_ppc_half16:
switch (Modifier) {
default: llvm_unreachable("Unsupported Modifier");
case MCSymbolRefExpr::VK_None:
Type = ELF::R_PPC_REL16;
break;
case MCSymbolRefExpr::VK_PPC_LO:
Type = ELF::R_PPC_REL16_LO;
break;
case MCSymbolRefExpr::VK_PPC_HI:
Type = ELF::R_PPC_REL16_HI;
break;
case MCSymbolRefExpr::VK_PPC_HA:
Type = ELF::R_PPC_REL16_HA;
break;
}
break;
case FK_Data_4:
case FK_PCRel_4:
Type = ELF::R_PPC_REL32;

26
test/MC/PowerPC/ppc64-fixups.s
View File

@ -87,6 +87,32 @@
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO_DS target 0x0
ld 1, target@l(3)
# CHECK: ld 1, target(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 2, value: target, kind: fixup_ppc_half16ds
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_DS target 0x0
ld 1, target(3)
base:
# CHECK: li 3, target-base # encoding: [0x38,0x60,A,A]
# CHECK-NEXT: # fixup A - offset: 2, value: target-base, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_REL16 target 0x2
li 3, target-base
# CHECK: li 3, target-base@h # encoding: [0x38,0x60,A,A]
# CHECK-NEXT: # fixup A - offset: 2, value: target-base@h, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_REL16_HI target 0x6
li 3, target-base@h
# CHECK: li 3, target-base@l # encoding: [0x38,0x60,A,A]
# CHECK-NEXT: # fixup A - offset: 2, value: target-base@l, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_REL16_LO target 0xA
li 3, target-base@l
# CHECK: li 3, target-base@ha # encoding: [0x38,0x60,A,A]
# CHECK-NEXT: # fixup A - offset: 2, value: target-base@ha, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_REL16_HA target 0xE
li 3, target-base@ha
# CHECK: ld 1, target@toc(2) # encoding: [0xe8,0x22,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 2, value: target@toc, kind: fixup_ppc_half16ds
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_DS target 0x0