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Remove code which is no longer needed in MipsAsmPrinter and MipsMCInstLower.

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llvm-svn: 157867
This commit is contained in:
Akira Hatanaka 2012-06-02 00:05:11 +00:00
parent 334dbca66f
commit 378d42a0b3
3 changed files with 0 additions and 171 deletions
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57
lib/Target/Mips/MipsAsmPrinter.cpp
View File

@ -43,19 +43,6 @@
using namespace llvm;
void MipsAsmPrinter::EmitInstrWithMacroNoAT(const MachineInstr *MI) {
MCInst TmpInst;
MCInstLowering.Lower(MI, TmpInst);
OutStreamer.EmitRawText(StringRef("\t.set\tmacro"));
if (MipsFI->getEmitNOAT())
OutStreamer.EmitRawText(StringRef("\t.set\tat"));
OutStreamer.EmitInstruction(TmpInst);
if (MipsFI->getEmitNOAT())
OutStreamer.EmitRawText(StringRef("\t.set\tnoat"));
OutStreamer.EmitRawText(StringRef("\t.set\tnomacro"));
}
bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
MipsFI = MF.getInfo<MipsFunctionInfo>();
AsmPrinter::runOnMachineFunction(MF);
@ -71,51 +58,7 @@ void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
return;
}
unsigned Opc = MI->getOpcode();
MCInst TmpInst0;
SmallVector<MCInst, 4> MCInsts;
switch (Opc) {
case Mips::ULW:
case Mips::ULH:
case Mips::ULHu:
case Mips::USW:
case Mips::USH:
case Mips::ULW_P8:
case Mips::ULH_P8:
case Mips::ULHu_P8:
case Mips::USW_P8:
case Mips::USH_P8:
case Mips::ULD:
case Mips::ULW64:
case Mips::ULH64:
case Mips::ULHu64:
case Mips::USD:
case Mips::USW64:
case Mips::USH64:
case Mips::ULD_P8:
case Mips::ULW64_P8:
case Mips::ULH64_P8:
case Mips::ULHu64_P8:
case Mips::USD_P8:
case Mips::USW64_P8:
case Mips::USH64_P8: {
if (OutStreamer.hasRawTextSupport()) {
EmitInstrWithMacroNoAT(MI);
return;
}
MCInstLowering.LowerUnalignedLoadStore(MI, MCInsts);
for (SmallVector<MCInst, 4>::iterator I = MCInsts.begin(); I
!= MCInsts.end(); ++I)
OutStreamer.EmitInstruction(*I);
return;
}
default:
break;
}
MCInstLowering.Lower(MI, TmpInst0);
OutStreamer.EmitInstruction(TmpInst0);
}

112
lib/Target/Mips/MipsMCInstLower.cpp
View File

@ -157,118 +157,6 @@ void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
}
}
void MipsMCInstLower::LowerUnalignedLoadStore(const MachineInstr *MI,
SmallVector<MCInst,
4>& MCInsts) {
unsigned Opc = MI->getOpcode();
MCInst Instr1, Instr2, Instr3, Move;
bool TwoInstructions = false;
assert(MI->getNumOperands() == 3);
assert(MI->getOperand(0).isReg());
assert(MI->getOperand(1).isReg());
MCOperand Target = LowerOperand(MI->getOperand(0));
MCOperand Base = LowerOperand(MI->getOperand(1));
MCOperand ATReg = MCOperand::CreateReg(Mips::AT);
MCOperand ZeroReg = MCOperand::CreateReg(Mips::ZERO);
MachineOperand UnLoweredName = MI->getOperand(2);
MCOperand Name = LowerOperand(UnLoweredName);
Move.setOpcode(Mips::ADDu);
Move.addOperand(Target);
Move.addOperand(ATReg);
Move.addOperand(ZeroReg);
switch (Opc) {
case Mips::ULW: {
// FIXME: only works for little endian right now
MCOperand AdjName = LowerOperand(UnLoweredName, 3);
if (Base.getReg() == (Target.getReg())) {
Instr1.setOpcode(Mips::LWL);
Instr1.addOperand(ATReg);
Instr1.addOperand(Base);
Instr1.addOperand(AdjName);
Instr2.setOpcode(Mips::LWR);
Instr2.addOperand(ATReg);
Instr2.addOperand(Base);
Instr2.addOperand(Name);
Instr3 = Move;
} else {
TwoInstructions = true;
Instr1.setOpcode(Mips::LWL);
Instr1.addOperand(Target);
Instr1.addOperand(Base);
Instr1.addOperand(AdjName);
Instr2.setOpcode(Mips::LWR);
Instr2.addOperand(Target);
Instr2.addOperand(Base);
Instr2.addOperand(Name);
}
break;
}
case Mips::ULHu: {
// FIXME: only works for little endian right now
MCOperand AdjName = LowerOperand(UnLoweredName, 1);
Instr1.setOpcode(Mips::LBu);
Instr1.addOperand(ATReg);
Instr1.addOperand(Base);
Instr1.addOperand(AdjName);
Instr2.setOpcode(Mips::LBu);
Instr2.addOperand(Target);
Instr2.addOperand(Base);
Instr2.addOperand(Name);
Instr3.setOpcode(Mips::INS);
Instr3.addOperand(Target);
Instr3.addOperand(ATReg);
Instr3.addOperand(MCOperand::CreateImm(0x8));
Instr3.addOperand(MCOperand::CreateImm(0x18));
break;
}
case Mips::USW: {
// FIXME: only works for little endian right now
assert (Base.getReg() != Target.getReg());
TwoInstructions = true;
MCOperand AdjName = LowerOperand(UnLoweredName, 3);
Instr1.setOpcode(Mips::SWL);
Instr1.addOperand(Target);
Instr1.addOperand(Base);
Instr1.addOperand(AdjName);
Instr2.setOpcode(Mips::SWR);
Instr2.addOperand(Target);
Instr2.addOperand(Base);
Instr2.addOperand(Name);
break;
}
case Mips::USH: {
MCOperand AdjName = LowerOperand(UnLoweredName, 1);
Instr1.setOpcode(Mips::SB);
Instr1.addOperand(Target);
Instr1.addOperand(Base);
Instr1.addOperand(Name);
Instr2.setOpcode(Mips::SRL);
Instr2.addOperand(ATReg);
Instr2.addOperand(Target);
Instr2.addOperand(MCOperand::CreateImm(8));
Instr3.setOpcode(Mips::SB);
Instr3.addOperand(ATReg);
Instr3.addOperand(Base);
Instr3.addOperand(AdjName);
break;
}
default:
// FIXME: need to add others
llvm_unreachable("unaligned instruction not processed");
}
MCInsts.push_back(Instr1);
MCInsts.push_back(Instr2);
if (!TwoInstructions) MCInsts.push_back(Instr3);
}
// Create the following two instructions:
// "lui $2, %hi(_gp_disp)"
// "addiu $2, $2, %lo(_gp_disp)"

2
lib/Target/Mips/MipsMCInstLower.h
View File

@ -33,8 +33,6 @@ public:
MipsMCInstLower(MipsAsmPrinter &asmprinter);
void Initialize(Mangler *mang, MCContext* C);
void Lower(const MachineInstr *MI, MCInst &OutMI) const;
void LowerUnalignedLoadStore(const MachineInstr *MI,
SmallVector<MCInst, 4>& MCInsts);
void LowerSETGP01(SmallVector<MCInst, 4>& MCInsts);
private:
MCOperand LowerSymbolOperand(const MachineOperand &MO,