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[ARM] Add patterns for VADD with q and r registers

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Added support for VADD to use q and r registers, which reduces pressure
on q registers.

llvm-svn: 371230
This commit is contained in:
Oliver Cruickshank 2019-09-06 17:02:35 +00:00
parent 9378ede3d6
commit 379accace0
2 changed files with 83 additions and 0 deletions
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9
lib/Target/ARM/ARMInstrMVE.td
View File

@ -3599,6 +3599,15 @@ defm MVE_VSUB_qr_i : MVE_VADDSUB_qr_sizes<"vsub", "i", 0b0, 0b1, 0b1, 0b0>;
defm MVE_VQSUB_qr_s : MVE_VADDSUB_qr_sizes<"vqsub", "s", 0b1, 0b1, 0b0, 0b0>;
defm MVE_VQSUB_qr_u : MVE_VADDSUB_qr_sizes<"vqsub", "u", 0b1, 0b1, 0b0, 0b1>;
let Predicates = [HasMVEInt] in {
def : Pat<(v16i8 (add (v16i8 MQPR:$val1), (v16i8 (ARMvdup GPR:$val2)))),
(v16i8 (MVE_VADD_qr_i8 (v16i8 MQPR:$val1), (i32 GPR:$val2)))>;
def : Pat<(v8i16 (add (v8i16 MQPR:$val1), (v8i16 (ARMvdup GPR:$val2)))),
(v8i16 (MVE_VADD_qr_i16 (v8i16 MQPR:$val1), (i32 GPR:$val2)))>;
def : Pat<(v4i32 (add (v4i32 MQPR:$val1), (v4i32 (ARMvdup GPR:$val2)))),
(v4i32 (MVE_VADD_qr_i32 (v4i32 MQPR:$val1), (i32 GPR:$val2)))>;
}
class MVE_VQDMULL_qr<string iname, string suffix, bit size,
bit T, list<dag> pattern=[]>
: MVE_qDest_rSrc<iname, suffix, pattern> {

74
test/CodeGen/Thumb2/mve-vaddqr.ll Normal file
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@ -0,0 +1,74 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s
define arm_aapcs_vfpcc <4 x i32> @vaddqr_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: vaddqr_v4i32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.i32 q0, q0, r0
; CHECK-NEXT: bx lr
entry:
%i = insertelement <4 x i32> undef, i32 %src2, i32 0
%sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
%c = add <4 x i32> %src, %sp
ret <4 x i32> %c
}
define arm_aapcs_vfpcc <8 x i16> @vaddqr_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: vaddqr_v8i16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.i16 q0, q0, r0
; CHECK-NEXT: bx lr
entry:
%i = insertelement <8 x i16> undef, i16 %src2, i32 0
%sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
%c = add <8 x i16> %src, %sp
ret <8 x i16> %c
}
define arm_aapcs_vfpcc <16 x i8> @vaddqr_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: vaddqr_v16i8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.i8 q0, q0, r0
; CHECK-NEXT: bx lr
entry:
%i = insertelement <16 x i8> undef, i8 %src2, i32 0
%sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
%c = add <16 x i8> %src, %sp
ret <16 x i8> %c
}
define arm_aapcs_vfpcc <4 x i32> @vaddqr_v4i32_2(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: vaddqr_v4i32_2:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.i32 q0, q0, r0
; CHECK-NEXT: bx lr
entry:
%i = insertelement <4 x i32> undef, i32 %src2, i32 0
%sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
%c = add <4 x i32> %sp, %src
ret <4 x i32> %c
}
define arm_aapcs_vfpcc <8 x i16> @vaddqr_v8i16_2(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: vaddqr_v8i16_2:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.i16 q0, q0, r0
; CHECK-NEXT: bx lr
entry:
%i = insertelement <8 x i16> undef, i16 %src2, i32 0
%sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
%c = add <8 x i16> %sp, %src
ret <8 x i16> %c
}
define arm_aapcs_vfpcc <16 x i8> @vaddqr_v16i8_2(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: vaddqr_v16i8_2:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.i8 q0, q0, r0
; CHECK-NEXT: bx lr
entry:
%i = insertelement <16 x i8> undef, i8 %src2, i32 0
%sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
%c = add <16 x i8> %sp, %src
ret <16 x i8> %c
}