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Add all the rest of the ADD and SUB variants, some of which are important for
64-bit support. llvm-svn: 18087
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@ -116,13 +116,24 @@ def SRArr : F3_1<2, 0b100111, "sra">;
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def SRAri : F3_2<2, 0b100111, "sra">;
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// Section B.13 - Add Instructions, p. 108
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def ADDrr : F3_1<2, 0b000000, "add">;
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def ADDri : F3_2<2, 0b000000, "add">;
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def ADDrr : F3_1<2, 0b000000, "add">;
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def ADDri : F3_2<2, 0b000000, "add">;
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def ADDCCrr : F3_1<2, 0b010000, "addcc">;
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def ADDCCri : F3_2<2, 0b010000, "addcc">;
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def ADDXrr : F3_1<2, 0b001000, "addx">;
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def ADDXri : F3_2<2, 0b001000, "addx">;
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def ADDXCCrr: F3_1<2, 0b011000, "addxcc">;
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def ADDXCCri: F3_2<2, 0b011000, "addxcc">;
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// Section B.15 - Subtract Instructions, p. 110
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def SUBrr : F3_1<2, 0b000100, "sub">;
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def SUBri : F3_2<2, 0b000100, "sub">;
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def SUBCCrr : F3_1<2, 0b010100, "subcc">;
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def SUBCCri : F3_2<2, 0b010100, "subcc">;
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def SUBXrr : F3_1<2, 0b001100, "subx">;
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def SUBXri : F3_2<2, 0b001100, "subx">;
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def SUBXCCrr: F3_1<2, 0b011100, "subxcc">;
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def SUBXCCri: F3_2<2, 0b011100, "subxcc">;
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// Section B.18 - Multiply Instructions, p. 113
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def UMULrr : F3_1<2, 0b001010, "umul">;
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