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Try schedule def + use closer whne Sethi-Ullman numbers are the same.
e.g. t1 = op t2, c1 t3 = op t4, c2 and the following instructions are both ready. t2 = op c3 t4 = op c4 Then schedule t2 = op first. i.e. t4 = op c4 t2 = op c3 t1 = op t2, c1 t3 = op t4, c2 This creates more short live intervals which work better with the register allocator. llvm-svn: 35089
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@ -576,6 +576,15 @@ namespace {
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};
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}
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static unsigned closestSucc(const SUnit *SU) {
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unsigned MaxCycle = 0;
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for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I)
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if (I->first->Cycle > MaxCycle)
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MaxCycle = I->first->Cycle;
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return MaxCycle;
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}
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// Bottom up
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bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
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bool LIsTarget = left->Node->isTargetOpcode();
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@ -596,15 +605,38 @@ bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
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unsigned RPriority = SPQ->getNodePriority(right);
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if (LPriority > RPriority)
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return true;
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else if (LPriority == RPriority)
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if (left->Height > right->Height)
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else if (LPriority == RPriority) {
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// Try schedule def + use closer whne Sethi-Ullman numbers are the same.
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// e.g.
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// t1 = op t2, c1
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// t3 = op t4, c2
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//
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// and the following instructions are both ready.
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// t2 = op c3
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// t4 = op c4
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//
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// Then schedule t2 = op first.
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// i.e.
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// t4 = op c4
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// t2 = op c3
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// t1 = op t2, c1
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// t3 = op t4, c2
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//
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// This creates more short live intervals.
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unsigned LDist = closestSucc(left);
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unsigned RDist = closestSucc(right);
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if (LDist < RDist)
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return true;
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else if (left->Height == right->Height)
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if (left->Depth < right->Depth)
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else if (LDist == RDist)
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if (left->Height > right->Height)
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return true;
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else if (left->Depth == right->Depth)
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if (left->CycleBound > right->CycleBound)
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else if (left->Height == right->Height)
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if (left->Depth < right->Depth)
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return true;
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else if (left->Depth == right->Depth)
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if (left->CycleBound > right->CycleBound)
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return true;
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}
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return false;
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}
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