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Prevent generation of redundant addiu instructions that compute address of

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static variables or functions. 

llvm-svn: 133803
This commit is contained in:
Akira Hatanaka 2011-06-24 17:55:19 +00:00
parent 5e20d4dbfc
commit 3a3e7dfd84
4 changed files with 7 additions and 6 deletions
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3
lib/Target/Mips/MipsISelDAGToDAG.cpp
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@ -170,7 +170,8 @@ SelectAddr(SDValue Addr, SDValue &Offset, SDValue &Base) {
Addr.getOperand(0).getOpcode() == ISD::LOAD) && Addr.getOperand(0).getOpcode() == ISD::LOAD) &&
Addr.getOperand(1).getOpcode() == MipsISD::Lo) { Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
SDValue LoVal = Addr.getOperand(1); SDValue LoVal = Addr.getOperand(1);
if (dyn_cast<ConstantPoolSDNode>(LoVal.getOperand(0))) { if (isa<ConstantPoolSDNode>(LoVal.getOperand(0)) ||
isa<GlobalAddressSDNode>(LoVal.getOperand(0))) {
Base = Addr.getOperand(0); Base = Addr.getOperand(0);
Offset = LoVal.getOperand(0); Offset = LoVal.getOperand(0);
return true; return true;

2
test/CodeGen/Mips/2008-07-15-SmallSection.ll
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@ -7,7 +7,7 @@
; RUN: not grep {sbss} %t1 ; RUN: not grep {sbss} %t1
; RUN: not grep {gp_rel} %t1 ; RUN: not grep {gp_rel} %t1
; RUN: grep {\%hi} %t1 | count 2 ; RUN: grep {\%hi} %t1 | count 2
; RUN: grep {\%lo} %t1 | count 2 ; RUN: grep {\%lo} %t1 | count 3
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "mipsallegrexel-unknown-psp-elf" target triple = "mipsallegrexel-unknown-psp-elf"

6
test/CodeGen/Mips/internalfunc.ll
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@ -15,7 +15,7 @@ entry:
define void @caller(i32 %a0, i32 %a1) nounwind { define void @caller(i32 %a0, i32 %a1) nounwind {
entry: entry:
; CHECK: lw $[[R1:[0-9]+]], %got(caller.sf1)($gp) ; CHECK: lw $[[R1:[0-9]+]], %got(caller.sf1)($gp)
; CHECK: addiu ${{[0-9]+}}, $[[R1]], %lo(caller.sf1) ; CHECK: lw $25, %lo(caller.sf1)($[[R1]])
%tobool = icmp eq i32 %a1, 0 %tobool = icmp eq i32 %a1, 0
br i1 %tobool, label %if.end, label %if.then br i1 %tobool, label %if.end, label %if.then
@ -26,9 +26,9 @@ if.then: ; preds = %entry
if.end: ; preds = %entry, %if.then if.end: ; preds = %entry, %if.then
; CHECK: lw $[[R2:[0-9]+]], %got(sf2)($gp) ; CHECK: lw $[[R2:[0-9]+]], %got(sf2)($gp)
; CHECK: lw $[[R3:[0-9]+]], %got(caller.sf1)($gp)
; CHECK: addiu ${{[0-9]+}}, $[[R2]], %lo(sf2) ; CHECK: addiu ${{[0-9]+}}, $[[R2]], %lo(sf2)
; CHECK: addiu ${{[0-9]+}}, $[[R3]], %lo(caller.sf1) ; CHECK: lw $[[R3:[0-9]+]], %got(caller.sf1)($gp)
; CHECK: sw ${{[0-9]+}}, %lo(caller.sf1)($[[R3]])
%tobool3 = icmp ne i32 %a0, 0 %tobool3 = icmp ne i32 %a0, 0
%tmp4 = load void (...)** @gf1, align 4 %tmp4 = load void (...)** @gf1, align 4
%cond = select i1 %tobool3, void (...)* %tmp4, void (...)* bitcast (void ()* @sf2 to void (...)*) %cond = select i1 %tobool3, void (...)* %tmp4, void (...)* bitcast (void ()* @sf2 to void (...)*)

2
test/CodeGen/Mips/o32_cc_byval.ll
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@ -24,7 +24,7 @@ entry:
; CHECK: sw $[[R4]], 28($sp) ; CHECK: sw $[[R4]], 28($sp)
; CHECK: sw $[[R5]], 32($sp) ; CHECK: sw $[[R5]], 32($sp)
; CHECK: sw $[[R6]], 36($sp) ; CHECK: sw $[[R6]], 36($sp)
; CHECK: lw $6, 0($[[R0]]) ; CHECK: lw $6, %lo(f1.s1)($[[R1]])
; CHECK: lw $7, 4($[[R0]]) ; CHECK: lw $7, 4($[[R0]])
%agg.tmp10 = alloca %struct.S3, align 4 %agg.tmp10 = alloca %struct.S3, align 4
call void @callee1(float 2.000000e+01, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind call void @callee1(float 2.000000e+01, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind