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Fix a regression from r147481. This combine should only happen if there is a

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single use.
rdar://11360370

llvm-svn: 156316
This commit is contained in:
Chad Rosier 2012-05-07 18:47:44 +00:00
parent ee7706f1a3
commit 3e284d8bd6
2 changed files with 14 additions and 11 deletions
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22
lib/Target/X86/X86ISelLowering.cpp
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@ -13050,16 +13050,18 @@ static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
// If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
SDValue ResNode =
DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
Ld->getMemoryVT(),
Ld->getPointerInfo(),
Ld->getAlignment(),
false/*isVolatile*/, true/*ReadMem*/,
false/*WriteMem*/);
return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
if (Ld->hasNUsesOfValue(1, 0)) {
SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
SDValue ResNode =
DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
Ld->getMemoryVT(),
Ld->getPointerInfo(),
Ld->getAlignment(),
false/*isVolatile*/, true/*ReadMem*/,
false/*WriteMem*/);
return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
}
}
// Emit a zeroed vector and insert the desired subvector on its

3
test/CodeGen/X86/2012-04-26-sdglue.ll
View File

@ -5,7 +5,8 @@
; It's hard to test for the ISEL condition because CodeGen optimizes
; away the bugpointed code. Just ensure the basics are still there.
;CHECK: func:
;CHECK: vmovups
;CHECK: vpxor
;CHECK: vinsertf128
;CHECK: vpshufd
;CHECK: vpshufd
;CHECK: vmulps