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[mips] Rename DSPRegs.
llvm-svn: 188342
This commit is contained in:
Akira Hatanaka
parent
6ac16b554b
commit
3e7c555daa
@ -103,10 +103,10 @@ static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeDSPRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
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unsigned RegNo,
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@ -359,10 +359,10 @@ static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeDSPRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
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}
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@ -515,35 +515,35 @@ class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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// Addition/subtraction
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class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", null_frag, NoItinerary,
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DSPRegs, DSPRegs>, IsCommutable,
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DSPR, DSPR>, IsCommutable,
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Defs<[DSPOutFlag20]>;
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class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb,
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NoItinerary, DSPRegs, DSPRegs>,
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NoItinerary, DSPR, DSPR>,
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IsCommutable, Defs<[DSPOutFlag20]>;
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class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag, NoItinerary,
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DSPRegs, DSPRegs>,
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DSPR, DSPR>,
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Defs<[DSPOutFlag20]>;
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class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb,
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NoItinerary, DSPRegs, DSPRegs>,
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NoItinerary, DSPR, DSPR>,
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Defs<[DSPOutFlag20]>;
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class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", null_frag, NoItinerary,
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DSPRegs, DSPRegs>, IsCommutable,
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DSPR, DSPR>, IsCommutable,
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Defs<[DSPOutFlag20]>;
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class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph,
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NoItinerary, DSPRegs, DSPRegs>,
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NoItinerary, DSPR, DSPR>,
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IsCommutable, Defs<[DSPOutFlag20]>;
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class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", null_frag, NoItinerary,
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DSPRegs, DSPRegs>,
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DSPR, DSPR>,
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Defs<[DSPOutFlag20]>;
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class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph,
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NoItinerary, DSPRegs, DSPRegs>,
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NoItinerary, DSPR, DSPR>,
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Defs<[DSPOutFlag20]>;
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class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,
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@ -566,11 +566,11 @@ class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary,
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GPR32, GPR32>;
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class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
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NoItinerary, GPR32, DSPRegs>;
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NoItinerary, GPR32, DSPR>;
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// Absolute value
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class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph,
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NoItinerary, DSPRegs>,
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NoItinerary, DSPR>,
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Defs<[DSPOutFlag20]>;
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class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w,
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@ -580,106 +580,106 @@ class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w,
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// Precision reduce/expand
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class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",
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int_mips_precrq_qb_ph,
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NoItinerary, DSPRegs, DSPRegs>;
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NoItinerary, DSPR, DSPR>;
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class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w",
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int_mips_precrq_ph_w,
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NoItinerary, DSPRegs, GPR32>;
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NoItinerary, DSPR, GPR32>;
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class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w",
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int_mips_precrq_rs_ph_w,
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NoItinerary, DSPRegs,
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NoItinerary, DSPR,
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GPR32>,
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Defs<[DSPOutFlag22]>;
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class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph",
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int_mips_precrqu_s_qb_ph,
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NoItinerary, DSPRegs,
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DSPRegs>,
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NoItinerary, DSPR,
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DSPR>,
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Defs<[DSPOutFlag22]>;
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class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl",
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int_mips_preceq_w_phl,
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NoItinerary, GPR32, DSPRegs>;
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NoItinerary, GPR32, DSPR>;
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class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr",
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int_mips_preceq_w_phr,
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NoItinerary, GPR32, DSPRegs>;
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NoItinerary, GPR32, DSPR>;
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class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl",
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int_mips_precequ_ph_qbl,
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NoItinerary, DSPRegs>;
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NoItinerary, DSPR>;
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class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr",
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int_mips_precequ_ph_qbr,
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NoItinerary, DSPRegs>;
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NoItinerary, DSPR>;
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class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla",
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int_mips_precequ_ph_qbla,
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NoItinerary, DSPRegs>;
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NoItinerary, DSPR>;
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class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra",
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int_mips_precequ_ph_qbra,
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NoItinerary, DSPRegs>;
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NoItinerary, DSPR>;
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class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl",
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int_mips_preceu_ph_qbl,
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NoItinerary, DSPRegs>;
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NoItinerary, DSPR>;
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class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr",
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int_mips_preceu_ph_qbr,
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NoItinerary, DSPRegs>;
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NoItinerary, DSPR>;
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class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla",
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int_mips_preceu_ph_qbla,
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NoItinerary, DSPRegs>;
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NoItinerary, DSPR>;
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class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra",
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int_mips_preceu_ph_qbra,
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NoItinerary, DSPRegs>;
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NoItinerary, DSPR>;
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// Shift
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class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", null_frag, immZExt3,
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NoItinerary, DSPRegs>,
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NoItinerary, DSPR>,
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Defs<[DSPOutFlag22]>;
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class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,
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NoItinerary, DSPRegs>,
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NoItinerary, DSPR>,
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Defs<[DSPOutFlag22]>;
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class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", null_frag, immZExt3,
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NoItinerary, DSPRegs>;
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NoItinerary, DSPR>;
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class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb,
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NoItinerary, DSPRegs>;
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NoItinerary, DSPR>;
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class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", null_frag, immZExt4,
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NoItinerary, DSPRegs>,
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NoItinerary, DSPR>,
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Defs<[DSPOutFlag22]>;
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class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph,
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NoItinerary, DSPRegs>,
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NoItinerary, DSPR>,
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Defs<[DSPOutFlag22]>;
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class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph,
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immZExt4, NoItinerary, DSPRegs>,
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immZExt4, NoItinerary, DSPR>,
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Defs<[DSPOutFlag22]>;
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class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph,
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NoItinerary, DSPRegs>,
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NoItinerary, DSPR>,
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Defs<[DSPOutFlag22]>;
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class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", null_frag, immZExt4,
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NoItinerary, DSPRegs>;
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NoItinerary, DSPR>;
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class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph,
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NoItinerary, DSPRegs>;
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NoItinerary, DSPR>;
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class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph,
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immZExt4, NoItinerary, DSPRegs>;
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immZExt4, NoItinerary, DSPR>;
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class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph,
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NoItinerary, DSPRegs>;
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NoItinerary, DSPR>;
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class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w,
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immZExt5, NoItinerary, GPR32>,
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@ -698,26 +698,26 @@ class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w,
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// Multiplication
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class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl",
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int_mips_muleu_s_ph_qbl,
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NoItinerary, DSPRegs, DSPRegs>,
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NoItinerary, DSPR, DSPR>,
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Defs<[DSPOutFlag21]>;
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class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr",
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int_mips_muleu_s_ph_qbr,
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NoItinerary, DSPRegs, DSPRegs>,
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NoItinerary, DSPR, DSPR>,
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Defs<[DSPOutFlag21]>;
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class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl",
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int_mips_muleq_s_w_phl,
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NoItinerary, GPR32, DSPRegs>,
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NoItinerary, GPR32, DSPR>,
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IsCommutable, Defs<[DSPOutFlag21]>;
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class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr",
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int_mips_muleq_s_w_phr,
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NoItinerary, GPR32, DSPRegs>,
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NoItinerary, GPR32, DSPR>,
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IsCommutable, Defs<[DSPOutFlag21]>;
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class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph,
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NoItinerary, DSPRegs, DSPRegs>,
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NoItinerary, DSPR, DSPR>,
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IsCommutable, Defs<[DSPOutFlag21]>;
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class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph",
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@ -773,40 +773,40 @@ class MSUBU_DSP_DESC : MADD_DESC_BASE<"msubu", MipsMSubu, NoItinerary>;
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// Comparison
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class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb",
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int_mips_cmpu_eq_qb, NoItinerary,
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DSPRegs>,
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DSPR>,
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IsCommutable, Defs<[DSPCCond]>;
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class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb",
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int_mips_cmpu_lt_qb, NoItinerary,
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DSPRegs>, Defs<[DSPCCond]>;
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DSPR>, Defs<[DSPCCond]>;
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class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb",
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int_mips_cmpu_le_qb, NoItinerary,
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DSPRegs>, Defs<[DSPCCond]>;
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DSPR>, Defs<[DSPCCond]>;
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class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb",
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int_mips_cmpgu_eq_qb,
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NoItinerary, GPR32, DSPRegs>,
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NoItinerary, GPR32, DSPR>,
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IsCommutable;
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class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb",
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int_mips_cmpgu_lt_qb,
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NoItinerary, GPR32, DSPRegs>;
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NoItinerary, GPR32, DSPR>;
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class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb",
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int_mips_cmpgu_le_qb,
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NoItinerary, GPR32, DSPRegs>;
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NoItinerary, GPR32, DSPR>;
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class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph,
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NoItinerary, DSPRegs>,
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NoItinerary, DSPR>,
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IsCommutable, Defs<[DSPCCond]>;
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class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph,
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NoItinerary, DSPRegs>,
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NoItinerary, DSPR>,
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Defs<[DSPCCond]>;
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class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph,
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NoItinerary, DSPRegs>,
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NoItinerary, DSPR>,
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Defs<[DSPCCond]>;
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// Misc
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@ -814,26 +814,26 @@ class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev,
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NoItinerary, GPR32>;
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class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph,
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NoItinerary, DSPRegs, DSPRegs>;
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NoItinerary, DSPR, DSPR>;
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class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, immZExt8,
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NoItinerary, DSPRegs>;
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NoItinerary, DSPR>;
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class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, immZExt10,
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NoItinerary, DSPRegs>;
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NoItinerary, DSPR>;
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class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
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NoItinerary, DSPRegs, GPR32>;
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NoItinerary, DSPR, GPR32>;
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class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,
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NoItinerary, DSPRegs, GPR32>;
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NoItinerary, DSPR, GPR32>;
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class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb,
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NoItinerary, DSPRegs, DSPRegs>,
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NoItinerary, DSPR, DSPR>,
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Uses<[DSPCCond]>;
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class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph,
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NoItinerary, DSPRegs, DSPRegs>,
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NoItinerary, DSPR, DSPR>,
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Uses<[DSPCCond]>;
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class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>;
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@ -905,44 +905,44 @@ class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>,
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// MIPS DSP Rev 2
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// Addition/subtraction
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class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary,
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DSPRegs, DSPRegs>, IsCommutable,
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DSPR, DSPR>, IsCommutable,
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Defs<[DSPOutFlag20]>;
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class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph,
|
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NoItinerary, DSPRegs, DSPRegs>,
|
||||
NoItinerary, DSPR, DSPR>,
|
||||
IsCommutable, Defs<[DSPOutFlag20]>;
|
||||
|
||||
class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,
|
||||
DSPRegs, DSPRegs>,
|
||||
DSPR, DSPR>,
|
||||
Defs<[DSPOutFlag20]>;
|
||||
|
||||
class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,
|
||||
NoItinerary, DSPRegs, DSPRegs>,
|
||||
NoItinerary, DSPR, DSPR>,
|
||||
Defs<[DSPOutFlag20]>;
|
||||
|
||||
class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb,
|
||||
NoItinerary, DSPRegs>, IsCommutable;
|
||||
NoItinerary, DSPR>, IsCommutable;
|
||||
|
||||
class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb,
|
||||
NoItinerary, DSPRegs>, IsCommutable;
|
||||
NoItinerary, DSPR>, IsCommutable;
|
||||
|
||||
class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb,
|
||||
NoItinerary, DSPRegs>;
|
||||
NoItinerary, DSPR>;
|
||||
|
||||
class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb,
|
||||
NoItinerary, DSPRegs>;
|
||||
NoItinerary, DSPR>;
|
||||
|
||||
class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph,
|
||||
NoItinerary, DSPRegs>, IsCommutable;
|
||||
NoItinerary, DSPR>, IsCommutable;
|
||||
|
||||
class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph,
|
||||
NoItinerary, DSPRegs>, IsCommutable;
|
||||
NoItinerary, DSPR>, IsCommutable;
|
||||
|
||||
class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph,
|
||||
NoItinerary, DSPRegs>;
|
||||
NoItinerary, DSPR>;
|
||||
|
||||
class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph,
|
||||
NoItinerary, DSPRegs>;
|
||||
NoItinerary, DSPR>;
|
||||
|
||||
class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w,
|
||||
NoItinerary, GPR32>, IsCommutable;
|
||||
@ -959,31 +959,31 @@ class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w,
|
||||
// Comparison
|
||||
class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb",
|
||||
int_mips_cmpgdu_eq_qb,
|
||||
NoItinerary, GPR32, DSPRegs>,
|
||||
NoItinerary, GPR32, DSPR>,
|
||||
IsCommutable, Defs<[DSPCCond]>;
|
||||
|
||||
class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb",
|
||||
int_mips_cmpgdu_lt_qb,
|
||||
NoItinerary, GPR32, DSPRegs>,
|
||||
NoItinerary, GPR32, DSPR>,
|
||||
Defs<[DSPCCond]>;
|
||||
|
||||
class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb",
|
||||
int_mips_cmpgdu_le_qb,
|
||||
NoItinerary, GPR32, DSPRegs>,
|
||||
NoItinerary, GPR32, DSPR>,
|
||||
Defs<[DSPCCond]>;
|
||||
|
||||
// Absolute
|
||||
class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb,
|
||||
NoItinerary, DSPRegs>,
|
||||
NoItinerary, DSPR>,
|
||||
Defs<[DSPOutFlag20]>;
|
||||
|
||||
// Multiplication
|
||||
class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", null_frag, NoItinerary,
|
||||
DSPRegs>, IsCommutable,
|
||||
DSPR>, IsCommutable,
|
||||
Defs<[DSPOutFlag21]>;
|
||||
|
||||
class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph,
|
||||
NoItinerary, DSPRegs>, IsCommutable,
|
||||
NoItinerary, DSPR>, IsCommutable,
|
||||
Defs<[DSPOutFlag21]>;
|
||||
|
||||
class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w,
|
||||
@ -995,7 +995,7 @@ class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w,
|
||||
Defs<[DSPOutFlag21]>;
|
||||
|
||||
class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
|
||||
NoItinerary, DSPRegs, DSPRegs>,
|
||||
NoItinerary, DSPR, DSPR>,
|
||||
IsCommutable, Defs<[DSPOutFlag21]>;
|
||||
|
||||
// Dot product with accumulate/subtract
|
||||
@ -1026,36 +1026,36 @@ class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph", MipsMULSA_W_PH>;
|
||||
// Precision reduce/expand
|
||||
class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph",
|
||||
int_mips_precr_qb_ph,
|
||||
NoItinerary, DSPRegs, DSPRegs>;
|
||||
NoItinerary, DSPR, DSPR>;
|
||||
|
||||
class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w",
|
||||
int_mips_precr_sra_ph_w,
|
||||
NoItinerary, DSPRegs,
|
||||
NoItinerary, DSPR,
|
||||
GPR32>;
|
||||
|
||||
class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w",
|
||||
int_mips_precr_sra_r_ph_w,
|
||||
NoItinerary, DSPRegs,
|
||||
NoItinerary, DSPR,
|
||||
GPR32>;
|
||||
|
||||
// Shift
|
||||
class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", null_frag, immZExt3,
|
||||
NoItinerary, DSPRegs>;
|
||||
NoItinerary, DSPR>;
|
||||
|
||||
class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb,
|
||||
NoItinerary, DSPRegs>;
|
||||
NoItinerary, DSPR>;
|
||||
|
||||
class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb,
|
||||
immZExt3, NoItinerary, DSPRegs>;
|
||||
immZExt3, NoItinerary, DSPR>;
|
||||
|
||||
class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb,
|
||||
NoItinerary, DSPRegs>;
|
||||
NoItinerary, DSPR>;
|
||||
|
||||
class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", null_frag, immZExt4,
|
||||
NoItinerary, DSPRegs>;
|
||||
NoItinerary, DSPR>;
|
||||
|
||||
class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph,
|
||||
NoItinerary, DSPRegs>;
|
||||
NoItinerary, DSPR>;
|
||||
|
||||
// Misc
|
||||
class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, immZExt5,
|
||||
@ -1252,12 +1252,12 @@ let isPseudo = 1, isCodeGenOnly = 1 in {
|
||||
|
||||
// Pseudo CMP and PICK instructions.
|
||||
class PseudoCMP<Instruction RealInst> :
|
||||
PseudoDSP<(outs DSPCC:$cmp), (ins DSPRegs:$rs, DSPRegs:$rt), []>,
|
||||
PseudoInstExpansion<(RealInst DSPRegs:$rs, DSPRegs:$rt)>, NeverHasSideEffects;
|
||||
PseudoDSP<(outs DSPCC:$cmp), (ins DSPR:$rs, DSPR:$rt), []>,
|
||||
PseudoInstExpansion<(RealInst DSPR:$rs, DSPR:$rt)>, NeverHasSideEffects;
|
||||
|
||||
class PseudoPICK<Instruction RealInst> :
|
||||
PseudoDSP<(outs DSPRegs:$rd), (ins DSPCC:$cmp, DSPRegs:$rs, DSPRegs:$rt), []>,
|
||||
PseudoInstExpansion<(RealInst DSPRegs:$rd, DSPRegs:$rs, DSPRegs:$rt)>,
|
||||
PseudoDSP<(outs DSPR:$rd), (ins DSPCC:$cmp, DSPR:$rs, DSPR:$rt), []>,
|
||||
PseudoInstExpansion<(RealInst DSPR:$rd, DSPR:$rs, DSPR:$rt)>,
|
||||
NeverHasSideEffects;
|
||||
|
||||
def PseudoCMP_EQ_PH : PseudoCMP<CMP_EQ_PH>;
|
||||
@ -1279,19 +1279,19 @@ class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
|
||||
DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
|
||||
(COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
|
||||
|
||||
def : BitconvertPat<i32, v2i16, GPR32, DSPRegs>;
|
||||
def : BitconvertPat<i32, v4i8, GPR32, DSPRegs>;
|
||||
def : BitconvertPat<v2i16, i32, DSPRegs, GPR32>;
|
||||
def : BitconvertPat<v4i8, i32, DSPRegs, GPR32>;
|
||||
def : BitconvertPat<i32, v2i16, GPR32, DSPR>;
|
||||
def : BitconvertPat<i32, v4i8, GPR32, DSPR>;
|
||||
def : BitconvertPat<v2i16, i32, DSPR, GPR32>;
|
||||
def : BitconvertPat<v4i8, i32, DSPR, GPR32>;
|
||||
|
||||
def : DSPPat<(v2i16 (load addr:$a)),
|
||||
(v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
|
||||
(v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
|
||||
def : DSPPat<(v4i8 (load addr:$a)),
|
||||
(v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
|
||||
def : DSPPat<(store (v2i16 DSPRegs:$val), addr:$a),
|
||||
(SW (COPY_TO_REGCLASS DSPRegs:$val, GPR32), addr:$a)>;
|
||||
def : DSPPat<(store (v4i8 DSPRegs:$val), addr:$a),
|
||||
(SW (COPY_TO_REGCLASS DSPRegs:$val, GPR32), addr:$a)>;
|
||||
(v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
|
||||
def : DSPPat<(store (v2i16 DSPR:$val), addr:$a),
|
||||
(SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
|
||||
def : DSPPat<(store (v4i8 DSPR:$val), addr:$a),
|
||||
(SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
|
||||
|
||||
// Binary operations.
|
||||
class DSPBinPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
|
||||
@ -1336,7 +1336,7 @@ class DSPSetCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
|
||||
CondCode CC> :
|
||||
DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
|
||||
(ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
|
||||
(ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPRegs)),
|
||||
(ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR)),
|
||||
(ValTy ZERO)))>;
|
||||
|
||||
class DSPSetCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
|
||||
@ -1344,7 +1344,7 @@ class DSPSetCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
|
||||
DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
|
||||
(ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
|
||||
(ValTy ZERO),
|
||||
(ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPRegs))))>;
|
||||
(ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR))))>;
|
||||
|
||||
class DSPSelectCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
|
||||
CondCode CC> :
|
||||
|
||||
@ -56,7 +56,7 @@ MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
|
||||
return 0;
|
||||
case Mips::GPR32RegClassID:
|
||||
case Mips::GPR64RegClassID:
|
||||
case Mips::DSPRegsRegClassID: {
|
||||
case Mips::DSPRRegClassID: {
|
||||
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
||||
return 28 - TFI->hasFP(MF);
|
||||
}
|
||||
|
||||
@ -279,7 +279,7 @@ class GPR32Class<list<ValueType> regTypes> :
|
||||
K0, K1, GP, SP, FP, RA)>;
|
||||
|
||||
def GPR32 : GPR32Class<[i32]>;
|
||||
def DSPRegs : GPR32Class<[v4i8, v2i16]>;
|
||||
def DSPR : GPR32Class<[v4i8, v2i16]>;
|
||||
|
||||
def GPR64 : RegisterClass<"Mips", [i64], 64, (add
|
||||
// Reserved
|
||||
@ -425,6 +425,10 @@ def GPR64Opnd : RegisterOperand<GPR64> {
|
||||
let ParserMatchClass = GPR64AsmOperand;
|
||||
}
|
||||
|
||||
def DSPROpnd : RegisterOperand<DSPR> {
|
||||
let ParserMatchClass = GPR32AsmOperand;
|
||||
}
|
||||
|
||||
def CCROpnd : RegisterOperand<CCR> {
|
||||
let ParserMatchClass = CCRAsmOperand;
|
||||
}
|
||||
|
||||
@ -40,7 +40,7 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
|
||||
MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
|
||||
|
||||
for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
|
||||
addRegisterClass(VecTys[i], &Mips::DSPRegsRegClass);
|
||||
addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
|
||||
|
||||
// Expand all builtin opcodes.
|
||||
for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user