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Add intrinsics for the peek and endin instructions.

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llvm-svn: 135474
This commit is contained in:
Richard Osborne 2011-07-19 12:50:25 +00:00
parent 7c36f4590e
commit 409c0d7768
3 changed files with 28 additions and 1 deletions
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4
include/llvm/IntrinsicsXCore.td
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@ -65,6 +65,10 @@ let TargetPrefix = "xcore" in { // All intrinsics start with "llvm.xcore.".
[NoCapture<0>, NoCapture<1>]>; [NoCapture<0>, NoCapture<1>]>;
def int_xcore_setpsc : Intrinsic<[],[llvm_anyptr_ty, llvm_i32_ty], def int_xcore_setpsc : Intrinsic<[],[llvm_anyptr_ty, llvm_i32_ty],
[NoCapture<0>]>; [NoCapture<0>]>;
def int_xcore_peek : Intrinsic<[llvm_i32_ty],[llvm_anyptr_ty],
[NoCapture<0>]>;
def int_xcore_endin : Intrinsic<[llvm_i32_ty],[llvm_anyptr_ty],
[NoCapture<0>]>;
// Intrinsics for events. // Intrinsics for events.
def int_xcore_waitevent : Intrinsic<[llvm_ptr_ty],[], [IntrReadMem]>; def int_xcore_waitevent : Intrinsic<[llvm_ptr_ty],[], [IntrReadMem]>;

9
lib/Target/XCore/XCoreInstrInfo.td
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@ -871,7 +871,6 @@ def INITDP_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src),
[(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>; [(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>;
// Two operand long // Two operand long
// TODO endin, peek,
// getd, testlcl // getd, testlcl
def BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), def BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
"bitrev $dst, $src", "bitrev $dst, $src",
@ -917,6 +916,14 @@ def SETPSC_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2),
"setpsc res[$src1], $src2", "setpsc res[$src1], $src2",
[(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>; [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>;
def PEEK_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
"peek $dst, res[$src]",
[(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>;
def ENDIN_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
"endin $dst, res[$src]",
[(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>;
// One operand short // One operand short
// TODO edu, eeu, waitet, waitef, tstart, clrtp // TODO edu, eeu, waitet, waitef, tstart, clrtp
// setdp, setcp, setev, kcall // setdp, setcp, setev, kcall

16
test/CodeGen/XCore/resources.ll
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@ -22,6 +22,8 @@ declare void @llvm.xcore.eeu.p1i8(i8 addrspace(1)* %r)
declare void @llvm.xcore.setclk.p1i8.p1i8(i8 addrspace(1)* %a, i8 addrspace(1)* %b) declare void @llvm.xcore.setclk.p1i8.p1i8(i8 addrspace(1)* %a, i8 addrspace(1)* %b)
declare void @llvm.xcore.setrdy.p1i8.p1i8(i8 addrspace(1)* %a, i8 addrspace(1)* %b) declare void @llvm.xcore.setrdy.p1i8.p1i8(i8 addrspace(1)* %a, i8 addrspace(1)* %b)
declare void @llvm.xcore.setpsc.p1i8(i8 addrspace(1)* %r, i32 %value) declare void @llvm.xcore.setpsc.p1i8(i8 addrspace(1)* %r, i32 %value)
declare i32 @llvm.xcore.peek.p1i8(i8 addrspace(1)* %r)
declare i32 @llvm.xcore.endin.p1i8(i8 addrspace(1)* %r)
define i8 addrspace(1)* @getr() { define i8 addrspace(1)* @getr() {
; CHECK: getr: ; CHECK: getr:
@ -198,3 +200,17 @@ define void @setpsc(i8 addrspace(1)* %r, i32 %value) {
call void @llvm.xcore.setpsc.p1i8(i8 addrspace(1)* %r, i32 %value) call void @llvm.xcore.setpsc.p1i8(i8 addrspace(1)* %r, i32 %value)
ret void ret void
} }
define i32 @peek(i8 addrspace(1)* %r) {
; CHECK: peek:
; CHECK: peek r0, res[r0]
%result = call i32 @llvm.xcore.peek.p1i8(i8 addrspace(1)* %r)
ret i32 %result
}
define i32 @endin(i8 addrspace(1)* %r) {
; CHECK: endin:
; CHECK: endin r0, res[r0]
%result = call i32 @llvm.xcore.endin.p1i8(i8 addrspace(1)* %r)
ret i32 %result
}