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[ARM] Use reduction intrinsics for larger than legal reductions
The codegen for splitting a llvm.vector.reduction intrinsic into parts will be better than the codegen for the generic reductions. This will only directly effect when vectorization factors are specified by the user. Also added tests to make sure the codegen for larger reductions is OK. Differential Revision: https://reviews.llvm.org/D72257
This commit is contained in:
David Green
parent
d0e4729521
commit
40a053e4e5
@ -1364,7 +1364,8 @@ bool ARMTTIImpl::useReductionIntrinsic(unsigned Opcode, Type *Ty,
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return false;
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case Instruction::ICmp:
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case Instruction::Add:
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return ScalarBits < 64 && ScalarBits * Ty->getVectorNumElements() == 128;
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return ScalarBits < 64 &&
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(ScalarBits * Ty->getVectorNumElements()) % 128 == 0;
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default:
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llvm_unreachable("Unhandled reduction opcode");
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}
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@ -3,8 +3,11 @@
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declare i64 @llvm.experimental.vector.reduce.add.i64.v2i64(<2 x i64>)
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declare i32 @llvm.experimental.vector.reduce.add.i32.v4i32(<4 x i32>)
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declare i32 @llvm.experimental.vector.reduce.add.i32.v8i32(<8 x i32>)
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declare i16 @llvm.experimental.vector.reduce.add.i16.v8i16(<8 x i16>)
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declare i16 @llvm.experimental.vector.reduce.add.i16.v16i16(<16 x i16>)
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declare i8 @llvm.experimental.vector.reduce.add.i8.v16i8(<16 x i8>)
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declare i8 @llvm.experimental.vector.reduce.add.i8.v32i8(<32 x i8>)
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define arm_aapcs_vfpcc i64 @vaddv_v2i64_i64(<2 x i64> %s1) {
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; CHECK-LABEL: vaddv_v2i64_i64:
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@ -31,8 +34,19 @@ entry:
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ret i32 %r
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}
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define arm_aapcs_vfpcc i16 @vaddv_v16i16_i16(<8 x i16> %s1) {
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; CHECK-LABEL: vaddv_v16i16_i16:
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define arm_aapcs_vfpcc i32 @vaddv_v8i32_i32(<8 x i32> %s1) {
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; CHECK-LABEL: vaddv_v8i32_i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vadd.i32 q0, q0, q1
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; CHECK-NEXT: vaddv.u32 r0, q0
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; CHECK-NEXT: bx lr
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entry:
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%r = call i32 @llvm.experimental.vector.reduce.add.i32.v8i32(<8 x i32> %s1)
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ret i32 %r
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}
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define arm_aapcs_vfpcc i16 @vaddv_v8i16_i16(<8 x i16> %s1) {
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; CHECK-LABEL: vaddv_v8i16_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vaddv.u16 r0, q0
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; CHECK-NEXT: bx lr
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@ -41,6 +55,17 @@ entry:
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ret i16 %r
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}
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define arm_aapcs_vfpcc i16 @vaddv_v16i16_i16(<16 x i16> %s1) {
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; CHECK-LABEL: vaddv_v16i16_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vadd.i16 q0, q0, q1
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; CHECK-NEXT: vaddv.u16 r0, q0
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; CHECK-NEXT: bx lr
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entry:
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%r = call i16 @llvm.experimental.vector.reduce.add.i16.v16i16(<16 x i16> %s1)
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ret i16 %r
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}
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define arm_aapcs_vfpcc i8 @vaddv_v16i8_i8(<16 x i8> %s1) {
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; CHECK-LABEL: vaddv_v16i8_i8:
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; CHECK: @ %bb.0: @ %entry
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@ -51,6 +76,17 @@ entry:
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ret i8 %r
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}
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define arm_aapcs_vfpcc i8 @vaddv_v32i8_i8(<32 x i8> %s1) {
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; CHECK-LABEL: vaddv_v32i8_i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vadd.i8 q0, q0, q1
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; CHECK-NEXT: vaddv.u8 r0, q0
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; CHECK-NEXT: bx lr
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entry:
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%r = call i8 @llvm.experimental.vector.reduce.add.i8.v32i8(<32 x i8> %s1)
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ret i8 %r
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}
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define arm_aapcs_vfpcc i64 @vaddva_v2i64_i64(<2 x i64> %s1, i64 %x) {
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; CHECK-LABEL: vaddva_v2i64_i64:
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; CHECK: @ %bb.0: @ %entry
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@ -82,6 +118,18 @@ entry:
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ret i32 %r
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}
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define arm_aapcs_vfpcc i32 @vaddva_v8i32_i32(<8 x i32> %s1, i32 %x) {
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; CHECK-LABEL: vaddva_v8i32_i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vadd.i32 q0, q0, q1
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; CHECK-NEXT: vaddva.u32 r0, q0
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; CHECK-NEXT: bx lr
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entry:
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%t = call i32 @llvm.experimental.vector.reduce.add.i32.v8i32(<8 x i32> %s1)
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%r = add i32 %t, %x
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ret i32 %r
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}
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define arm_aapcs_vfpcc i16 @vaddva_v8i16_i16(<8 x i16> %s1, i16 %x) {
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; CHECK-LABEL: vaddva_v8i16_i16:
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; CHECK: @ %bb.0: @ %entry
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@ -93,6 +141,18 @@ entry:
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ret i16 %r
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}
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define arm_aapcs_vfpcc i16 @vaddva_v16i16_i16(<16 x i16> %s1, i16 %x) {
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; CHECK-LABEL: vaddva_v16i16_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vadd.i16 q0, q0, q1
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; CHECK-NEXT: vaddva.u16 r0, q0
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; CHECK-NEXT: bx lr
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entry:
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%t = call i16 @llvm.experimental.vector.reduce.add.i16.v16i16(<16 x i16> %s1)
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%r = add i16 %t, %x
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ret i16 %r
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}
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define arm_aapcs_vfpcc i8 @vaddva_v16i8_i8(<16 x i8> %s1, i8 %x) {
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; CHECK-LABEL: vaddva_v16i8_i8:
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; CHECK: @ %bb.0: @ %entry
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@ -103,3 +163,15 @@ entry:
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%r = add i8 %t, %x
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ret i8 %r
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}
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define arm_aapcs_vfpcc i8 @vaddva_v32i8_i8(<32 x i8> %s1, i8 %x) {
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; CHECK-LABEL: vaddva_v32i8_i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vadd.i8 q0, q0, q1
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; CHECK-NEXT: vaddva.u8 r0, q0
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; CHECK-NEXT: bx lr
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entry:
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%t = call i8 @llvm.experimental.vector.reduce.add.i8.v32i8(<32 x i8> %s1)
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%r = add i8 %t, %x
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ret i8 %r
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}
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62
test/Transforms/LoopVectorize/ARM/mve-reduce.ll
Normal file
62
test/Transforms/LoopVectorize/ARM/mve-reduce.ll
Normal file
@ -0,0 +1,62 @@
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; RUN: opt -loop-vectorize < %s -S -o - | FileCheck %s
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8.1m.main-arm-none-eabi"
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; CHECK-LABEL: check4
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; CHECK: call i32 @llvm.experimental.vector.reduce.add.v4i32
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define i32 @check4(i8* noalias nocapture readonly %A, i8* noalias nocapture readonly %B, i32 %n) #0 {
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entry:
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%cmp9 = icmp sgt i32 %n, 0
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br i1 %cmp9, label %for.body, label %for.cond.cleanup
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for.cond.cleanup: ; preds = %for.body, %entry
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%res.0.lcssa = phi i32 [ undef, %entry ], [ %add, %for.body ]
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ret i32 %res.0.lcssa
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for.body: ; preds = %entry, %for.body
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%i.011 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%res.010 = phi i32 [ %add, %for.body ], [ undef, %entry ]
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%arrayidx = getelementptr inbounds i8, i8* %A, i32 %i.011
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%0 = load i8, i8* %arrayidx, align 1
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%conv = sext i8 %0 to i32
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%arrayidx1 = getelementptr inbounds i8, i8* %B, i32 %i.011
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%1 = load i8, i8* %arrayidx1, align 1
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%conv2 = sext i8 %1 to i32
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%mul = mul nsw i32 %conv2, %conv
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%add = add nsw i32 %mul, %res.010
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%inc = add nuw nsw i32 %i.011, 1
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%exitcond = icmp eq i32 %inc, %n
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br i1 %exitcond, label %for.cond.cleanup, label %for.body
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}
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; CHECK-LABEL: check16
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; CHECK: call i32 @llvm.experimental.vector.reduce.add.v16i32
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define i32 @check16(i8* noalias nocapture readonly %A, i8* noalias nocapture readonly %B, i32 %n) #0 {
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entry:
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%cmp9 = icmp sgt i32 %n, 0
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br i1 %cmp9, label %for.body, label %for.cond.cleanup
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for.cond.cleanup: ; preds = %for.body, %entry
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%res.0.lcssa = phi i32 [ undef, %entry ], [ %add, %for.body ]
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ret i32 %res.0.lcssa
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for.body: ; preds = %entry, %for.body
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%i.011 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%res.010 = phi i32 [ %add, %for.body ], [ undef, %entry ]
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%arrayidx = getelementptr inbounds i8, i8* %A, i32 %i.011
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%0 = load i8, i8* %arrayidx, align 1
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%conv = sext i8 %0 to i32
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%arrayidx1 = getelementptr inbounds i8, i8* %B, i32 %i.011
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%1 = load i8, i8* %arrayidx1, align 1
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%conv2 = sext i8 %1 to i32
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%mul = mul nsw i32 %conv2, %conv
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%add = add nsw i32 %mul, %res.010
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%inc = add nuw nsw i32 %i.011, 1
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%exitcond = icmp eq i32 %inc, %n
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br i1 %exitcond, label %for.cond.cleanup, label %for.body, !llvm.loop !6
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}
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attributes #0 = { "target-features"="+mve" }
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!6 = distinct !{!6, !7}
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!7 = !{!"llvm.loop.vectorize.width", i32 16}
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