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[AArch64] Fix fast-isel of cbz of i1, i8, i16
This fixes a miscompilation in the AArch64 fast-isel which was triggered when a branch is based on an icmp with condition eq or ne, and type i1, i8 or i16. The cbz instruction compares the whole 32-bit register, so values with the bottom 1, 8 or 16 bits clear would cause the wrong branch to be taken. llvm-svn: 220553
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@ -2181,6 +2181,12 @@ bool AArch64FastISel::emitCompareAndBranch(const BranchInst *BI) {
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SrcReg = fastEmitInst_extractsubreg(MVT::i32, SrcReg, SrcIsKill,
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AArch64::sub_32);
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if ((BW < 32) && !IsBitTest) {
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EVT CmpEVT = TLI.getValueType(Ty, true);
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SrcReg =
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emitIntExt(CmpEVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ true);
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}
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// Emit the combined compare and branch instruction.
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SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs());
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MachineInstrBuilder MIB =
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@ -1,8 +1,9 @@
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; RUN: llc -fast-isel -fast-isel-abort -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck %s
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define i32 @icmp_eq_i1(i1 signext %a) {
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define i32 @icmp_eq_i1(i1 %a) {
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; CHECK-LABEL: icmp_eq_i1
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; CHECK: cbz w0, {{LBB.+_2}}
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; CHECK: and [[REG:w[0-9]+]], w0, #0x1
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; CHECK: cbz [[REG]], {{LBB.+_2}}
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%1 = icmp eq i1 %a, 0
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br i1 %1, label %bb1, label %bb2
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bb2:
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@ -11,9 +12,10 @@ bb1:
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ret i32 0
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}
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define i32 @icmp_eq_i8(i8 signext %a) {
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define i32 @icmp_eq_i8(i8 %a) {
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; CHECK-LABEL: icmp_eq_i8
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; CHECK: cbz w0, {{LBB.+_2}}
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; CHECK: uxtb [[REG:w[0-9]+]], w0
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; CHECK: cbz [[REG]], {{LBB.+_2}}
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%1 = icmp eq i8 %a, 0
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br i1 %1, label %bb1, label %bb2
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bb2:
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@ -22,9 +24,10 @@ bb1:
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ret i32 0
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}
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define i32 @icmp_eq_i16(i16 signext %a) {
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define i32 @icmp_eq_i16(i16 %a) {
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; CHECK-LABEL: icmp_eq_i16
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; CHECK: cbz w0, {{LBB.+_2}}
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; CHECK: uxth [[REG:w[0-9]+]], w0
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; CHECK: cbz [[REG]], {{LBB.+_2}}
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%1 = icmp eq i16 %a, 0
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br i1 %1, label %bb1, label %bb2
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bb2:
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