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Duplicated node may produce a non-physical register def.
llvm-svn: 62015
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84945aba0b
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@ -188,7 +188,7 @@ namespace llvm {
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DenseMap<SDValue, unsigned> &VRBaseMap);
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void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
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const TargetInstrDesc &II,
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const TargetInstrDesc &II, bool IsClone,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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/// BuildSchedUnits, AddSchedEdges - Helper functions for BuildSchedGraph.
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@ -157,8 +157,8 @@ unsigned ScheduleDAGSDNodes::getDstOfOnlyCopyToRegUse(SDNode *Node,
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}
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void ScheduleDAGSDNodes::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
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const TargetInstrDesc &II,
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DenseMap<SDValue, unsigned> &VRBaseMap) {
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const TargetInstrDesc &II, bool IsClone,
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DenseMap<SDValue, unsigned> &VRBaseMap) {
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assert(Node->getMachineOpcode() != TargetInstrInfo::IMPLICIT_DEF &&
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"IMPLICIT_DEF should have been handled as a special case elsewhere!");
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@ -192,6 +192,8 @@ void ScheduleDAGSDNodes::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
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}
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SDValue Op(Node, i);
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if (IsClone)
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VRBaseMap.erase(Op);
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bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
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isNew = isNew; // Silence compiler warning.
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assert(isNew && "Node emitted out of order - early");
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@ -487,7 +489,7 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone,
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// Add result register values for things that are defined by this
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// instruction.
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if (NumResults)
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CreateVirtualRegisters(Node, MI, II, VRBaseMap);
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CreateVirtualRegisters(Node, MI, II, IsClone, VRBaseMap);
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// Emit all of the actual operands of this instruction, adding them to the
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// instruction as appropriate.
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41
test/CodeGen/X86/2009-01-09-SchedDupBug.ll
Normal file
41
test/CodeGen/X86/2009-01-09-SchedDupBug.ll
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@ -0,0 +1,41 @@
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; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
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; rdar://6481994
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%Value = type { i32 (...)** }
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declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) nounwind
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define %Value* @bar(%Value** %exception) nounwind {
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prologue:
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br i1 true, label %NextVerify41, label %FailedVerify
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NextVerify41: ; preds = %prologue
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br i1 true, label %NextVerify, label %FailedVerify
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NextVerify: ; preds = %NextVerify41
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br i1 false, label %label12, label %label
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label: ; preds = %NextVerify
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br i1 true, label %xxNumberLiteral.exit, label %handle_exception
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xxNumberLiteral.exit: ; preds = %label
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%0 = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 0, i32 0) ; <{ i32, i1 }> [#uses=2]
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%intAdd = extractvalue { i32, i1 } %0, 0 ; <i32> [#uses=1]
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%intAddOverflow = extractvalue { i32, i1 } %0, 1 ; <i1> [#uses=1]
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%toint55 = ashr i32 %intAdd, 1 ; <i32> [#uses=1]
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%toFP56 = sitofp i32 %toint55 to double ; <double> [#uses=1]
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br i1 %intAddOverflow, label %exit, label %label12
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label12: ; preds = %xxNumberLiteral.exit, %NextVerify
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%var_lr1.0 = phi double [ %toFP56, %xxNumberLiteral.exit ], [ 0.000000e+00, %NextVerify ] ; <double> [#uses=0]
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unreachable
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exit: ; preds = %xxNumberLiteral.exit
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ret %Value* null
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FailedVerify: ; preds = %NextVerify41, %prologue
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ret %Value* null
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handle_exception: ; preds = %label
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ret %Value* undef
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}
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