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[ImplicitNullCheck] Add alias analysis usage
Summary: With this change ImplicitNullCheck optimization uses alias analysis and can use load/store memory access for implicit null check if there are other load/store before but memory accesses do not alias. Patch by Serguei Katkov! Reviewers: sanjoy Reviewed By: sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30331 llvm-svn: 296440
This commit is contained in:
Sanjoy Das
parent
3b4bcc0f56
commit
41d809825d
@ -153,6 +153,7 @@ class ImplicitNullChecks : public MachineFunctionPass {
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const TargetRegisterInfo *TRI = nullptr;
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AliasAnalysis *AA = nullptr;
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MachineModuleInfo *MMI = nullptr;
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MachineFrameInfo *MFI = nullptr;
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bool analyzeBlockForNullChecks(MachineBasicBlock &MBB,
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SmallVectorImpl<NullCheck> &NullCheckList);
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@ -160,18 +161,29 @@ class ImplicitNullChecks : public MachineFunctionPass {
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MachineBasicBlock *HandlerMBB);
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void rewriteNullChecks(ArrayRef<NullCheck> NullCheckList);
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enum SuitabilityResult { SR_Suitable, SR_Unsuitable, SR_Impossible };
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enum AliasResult {
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AR_NoAlias,
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AR_MayAlias,
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AR_WillAliasEverything
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};
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/// Returns AR_NoAlias if \p MI memory operation does not alias with
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/// \p PrevMI, AR_MayAlias if they may alias and AR_WillAliasEverything if
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/// they may alias and any further memory operation may alias with \p PrevMI.
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AliasResult areMemoryOpsAliased(MachineInstr &MI, MachineInstr *PrevMI);
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enum SuitabilityResult {
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SR_Suitable,
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SR_Unsuitable,
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SR_Impossible
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};
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/// Return SR_Suitable if \p MI a memory operation that can be used to
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/// implicitly null check the value in \p PointerReg, SR_Unsuitable if
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/// \p MI cannot be used to null check and SR_Impossible if there is
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/// no sense to continue lookup due to any other instruction will not be able
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/// to be used. \p PrevInsts is the set of instruction seen since
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/// the explicit null check on \p PointerReg. \p SeenLoad means that load
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/// instruction has been observed in \PrevInsts set.
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/// the explicit null check on \p PointerReg.
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SuitabilityResult isSuitableMemoryOp(MachineInstr &MI, unsigned PointerReg,
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ArrayRef<MachineInstr *> PrevInsts,
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bool &SeenLoad);
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ArrayRef<MachineInstr *> PrevInsts);
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/// Return true if \p FaultingMI can be hoisted from after the the
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/// instructions in \p InstsSeenSoFar to before them. Set \p Dependence to a
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@ -269,6 +281,7 @@ bool ImplicitNullChecks::runOnMachineFunction(MachineFunction &MF) {
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TII = MF.getSubtarget().getInstrInfo();
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TRI = MF.getRegInfo().getTargetRegisterInfo();
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MMI = &MF.getMMI();
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MFI = &MF.getFrameInfo();
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AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
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SmallVector<NullCheck, 16> NullCheckList;
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@ -292,47 +305,84 @@ static bool AnyAliasLiveIn(const TargetRegisterInfo *TRI,
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return false;
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}
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ImplicitNullChecks::AliasResult
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ImplicitNullChecks::areMemoryOpsAliased(MachineInstr &MI,
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MachineInstr *PrevMI) {
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// If it is not memory access, skip the check.
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if (!(PrevMI->mayStore() || PrevMI->mayLoad()))
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return AR_NoAlias;
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// Load-Load may alias
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if (!(MI.mayStore() || PrevMI->mayStore()))
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return AR_NoAlias;
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// We lost info, conservatively alias. If it was store then no sense to
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// continue because we won't be able to check against it further.
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if (MI.memoperands_empty())
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return MI.mayStore() ? AR_WillAliasEverything : AR_MayAlias;
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if (PrevMI->memoperands_empty())
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return PrevMI->mayStore() ? AR_WillAliasEverything : AR_MayAlias;
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for (MachineMemOperand *MMO1 : MI.memoperands()) {
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// MMO1 should have a value due it comes from operation we'd like to use
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// as implicit null check.
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assert(MMO1->getValue() && "MMO1 should have a Value!");
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for (MachineMemOperand *MMO2 : PrevMI->memoperands()) {
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if (const PseudoSourceValue *PSV = MMO2->getPseudoValue()) {
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if (PSV->mayAlias(MFI))
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return AR_MayAlias;
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continue;
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}
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llvm::AliasResult AAResult = AA->alias(
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MemoryLocation(MMO1->getValue(), MemoryLocation::UnknownSize,
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MMO1->getAAInfo()),
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MemoryLocation(MMO2->getValue(), MemoryLocation::UnknownSize,
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MMO2->getAAInfo()));
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if (AAResult != NoAlias)
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return AR_MayAlias;
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}
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}
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return AR_NoAlias;
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}
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ImplicitNullChecks::SuitabilityResult
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ImplicitNullChecks::isSuitableMemoryOp(MachineInstr &MI, unsigned PointerReg,
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ArrayRef<MachineInstr *> PrevInsts,
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bool &SeenLoad) {
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ArrayRef<MachineInstr *> PrevInsts) {
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int64_t Offset;
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unsigned BaseReg;
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// First, if it is a store and we saw load before we bail out
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// because we will not be able to re-order load-store without
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// using alias analysis.
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if (SeenLoad && MI.mayStore())
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return SR_Impossible;
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SeenLoad = SeenLoad || MI.mayLoad();
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// Without alias analysis we cannot re-order store with anything.
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// so if this instruction is not a candidate we should stop.
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SuitabilityResult Unsuitable = MI.mayStore() ? SR_Impossible : SR_Unsuitable;
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if (!TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI) ||
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BaseReg != PointerReg)
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return Unsuitable;
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return SR_Unsuitable;
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// We want the mem access to be issued at a sane offset from PointerReg,
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// so that if PointerReg is null then the access reliably page faults.
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if (!((MI.mayLoad() || MI.mayStore()) && !MI.isPredicable() &&
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Offset < PageSize))
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return Unsuitable;
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return SR_Unsuitable;
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// Finally, we need to make sure that the access instruction actually is
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// accessing from PointerReg, and there isn't some re-definition of PointerReg
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// between the compare and the memory access.
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// If PointerReg has been redefined before then there is no sense to continue
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// lookup due to this condition will fail for any further instruction.
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SuitabilityResult Suitable = SR_Suitable;
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for (auto *PrevMI : PrevInsts)
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for (auto &PrevMO : PrevMI->operands())
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for (auto &PrevMO : PrevMI->operands()) {
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if (PrevMO.isReg() && PrevMO.getReg() && PrevMO.isDef() &&
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TRI->regsOverlap(PrevMO.getReg(), PointerReg))
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return SR_Impossible;
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return SR_Suitable;
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// Check whether the current memory access aliases with previous one.
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// If we already found that it aliases then no need to continue.
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// But we continue base pointer check as it can result in SR_Impossible.
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if (Suitable == SR_Suitable) {
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AliasResult AR = areMemoryOpsAliased(MI, PrevMI);
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if (AR == AR_WillAliasEverything)
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return SR_Impossible;
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if (AR == AR_MayAlias)
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Suitable = SR_Unsuitable;
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}
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}
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return Suitable;
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}
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bool ImplicitNullChecks::canHoistInst(MachineInstr *FaultingMI,
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@ -503,15 +553,13 @@ bool ImplicitNullChecks::analyzeBlockForNullChecks(
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const unsigned PointerReg = MBP.LHS.getReg();
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SmallVector<MachineInstr *, 8> InstsSeenSoFar;
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bool SeenLoad = false;
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for (auto &MI : *NotNullSucc) {
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if (!canHandle(&MI) || InstsSeenSoFar.size() >= MaxInstsToConsider)
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return false;
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MachineInstr *Dependence;
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SuitabilityResult SR =
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isSuitableMemoryOp(MI, PointerReg, InstsSeenSoFar, SeenLoad);
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SuitabilityResult SR = isSuitableMemoryOp(MI, PointerReg, InstsSeenSoFar);
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if (SR == SR_Impossible)
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return false;
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if (SR == SR_Suitable &&
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@ -341,6 +341,30 @@
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ret void
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}
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define i32 @inc_store_and_load_no_alias(i32* noalias %ptr, i32* noalias %ptr2) {
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entry:
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%ptr_is_null = icmp eq i32* %ptr, null
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br i1 %ptr_is_null, label %is_null, label %not_null, !make.implicit !0
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not_null:
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ret i32 undef
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is_null:
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ret i32 undef
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}
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define i32 @inc_store_and_load_alias(i32* %ptr, i32* %ptr2) {
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entry:
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%ptr_is_null = icmp eq i32* %ptr, null
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br i1 %ptr_is_null, label %is_null, label %not_null, !make.implicit !0
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not_null:
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ret i32 undef
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is_null:
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ret i32 undef
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}
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attributes #0 = { "target-features"="+bmi,+bmi2" }
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!0 = !{}
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@ -645,7 +669,7 @@ body: |
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name: use_alternate_load_op
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# CHECK-LABEL: name: use_alternate_load_op
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# CHECK: bb.0.entry:
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# CHECK: %r10 = FAULTING_OP 1, %bb.2.is_null, {{[0-9]+}}, killed %rdi, 1, _, 0, _
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# CHECK: %rax = FAULTING_OP 1, %bb.2.is_null, {{[0-9]+}}, killed %rdi, 1, _, 0, _
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# CHECK-NEXT: JMP_1 %bb.1.not_null
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# CHECK: bb.1.not_null
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@ -666,9 +690,9 @@ body: |
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liveins: %rdi, %rsi
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%rcx = MOV64rm killed %rsi, 1, _, 0, _
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%rdx = AND64rm killed %rcx, %rdi, 1, _, 0, _, implicit-def dead %eflags
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%r10 = MOV64rm killed %rdi, 1, _, 0, _
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RETQ %r10d
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%rcx = AND64rm killed %rcx, %rdi, 1, _, 0, _, implicit-def dead %eflags
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%rax = MOV64rm killed %rdi, 1, _, 0, _
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RETQ %eax
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bb.2.is_null:
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%eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags
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@ -1207,3 +1231,69 @@ body: |
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RETQ
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...
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---
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name: inc_store_and_load_no_alias
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# CHECK-LABEL: inc_store_and_load_no_alias
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# CHECK: bb.0.entry:
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# CHECK: %eax = FAULTING_OP 1, %bb.2.is_null, {{[0-9]+}}, killed %rdi, 1, _, 0, _ :: (load 4 from %ir.ptr)
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# CHECK-NEXT: JMP_1 %bb.1.not_null
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# CHECK: bb.1.not_null
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '%rdi' }
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- { reg: '%rsi' }
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body: |
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bb.0.entry:
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successors: %bb.2.is_null, %bb.1.not_null
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liveins: %rdi, %rsi
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TEST64rr %rdi, %rdi, implicit-def %eflags
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JE_1 %bb.2.is_null, implicit killed %eflags
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bb.1.not_null:
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liveins: %rdi, %rsi
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MOV32mi killed %rsi, 1, _, 0, _, 3 :: (store 4 into %ir.ptr2)
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%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.ptr)
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RETQ %eax
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bb.2.is_null:
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%eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags
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RETQ %eax
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...
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---
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name: inc_store_and_load_alias
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# CHECK-LABEL: inc_store_and_load_alias
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# CHECK: bb.0.entry:
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# CHECK: TEST64rr %rdi, %rdi, implicit-def %eflags
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# CHECK-NEXT: JE_1 %bb.2.is_null, implicit killed %eflags
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# CHECK: bb.1.not_null
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '%rdi' }
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- { reg: '%rsi' }
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body: |
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bb.0.entry:
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successors: %bb.2.is_null, %bb.1.not_null
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liveins: %rdi, %rsi
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TEST64rr %rdi, %rdi, implicit-def %eflags
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JE_1 %bb.2.is_null, implicit killed %eflags
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bb.1.not_null:
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liveins: %rdi, %rsi
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MOV32mi killed %rsi, 1, _, 0, _, 3 :: (store 4 into %ir.ptr2)
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%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.ptr)
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RETQ %eax
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bb.2.is_null:
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%eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags
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RETQ %eax
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...
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